SYSCTRL address start \newline
\subsubsection{CHIPIDR}
Address: 0x40001000. Reset: 0x25290111
\newline 
Chip ID Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:0 & VAL & RO & Chip Identification.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{RDPR}
Address: 0x40001020. Reset: 0x00000000
\newline 
FLASH Read Protect Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & RDP & WR & Read Protect Enable Register.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{RAMIER}
Address: 0x40001100. Reset: 0x00000000
\newline 
RAM ECC Interrupt Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & RAMECC & WR & RAM ECC Interrupt Enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{RAMSR}
Address: 0x40001104. Reset: 0x00000000
\newline 
RAM ECC Interrupt Status Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:2 & Reserve & RO & Reserve.\\ \hline
        1:0 & ERR & RO & When read RAM, ECC detects 1 bit err in one word, and correct this err bit.\newline 0: NOERR. No ecc err. \newline 1: ERR1B. When read RAM, ECC detects 1 bit err, and correct this err bit. \newline 2: ERR2B. When read RAM, ECC detects 2 bit err.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{RAMSCLR}
Address: 0x40001108. Reset: 0x00000000
\newline 
RAM ECC Interrupt Status Clear Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & ERRCLR & WO & Write 1 clear RAMECCSR.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{RAMSYNDR}
Address: 0x40001110. Reset: 0x00000000
\newline 
RAM ECC Syndrome Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:7 & Reserve & RO & Reserve.\\ \hline
        6:0 & SYND & RO & ECC Syndrome, There are RAM ECC err if this val is not 0. Use syndrome can find witch bit err if RAMCCSR is 1;\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{RAMINJLR}
Address: 0x40001114. Reset: 0x00000000
\newline 
RAM ECC Inject Low Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:0 & INJL & WR & Note: only when DBGEN = 1, writing this value is effective. When this val is not 0, read ram will lead to ecc error. For example, if this value is 0x8, read ram will lead to 4th ram Bit error.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{RAMINJHR}
Address: 0x40001118. Reset: 0x00000000
\newline 
RAM ECC Interrupt Status Clear Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:7 & Reserve & RO & Reserve.\\ \hline
        6:0 & INJH & WR & Note: only when DBGEN = 1, writing this value is effective. When this val is not 0, read ram will lead to ecc error. For example, if this value is 0x8, read ram will lead to 36th ram Bit error.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{ADCTGSRCR}
Address: 0x40001200. Reset: 0x00000000
\newline 
ADC trig source select Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:4 & Reserve & RO & Reserve.\\ \hline
        3:0 & TGSRC & WR & adc trig select source.\newline 0: NOTG. No event trig\newline 1: PWM0TG. PWM0 event trig\newline 2: PWM1TG. PWM1 event trig\newline 3: PWM2TG. PWM2 event trig\newline 4: PWMALLTG. Any PWM event trig\newline 5: TIM0TG. TIM0 event trig\newline 6: TIM1TG. TIM1 event trig\newline 7: TIM2TG. TIM2 event trig\newline 8: PWM\_OVERFLOW\_TRG. PWM period overflow event trig\newline 9: GPIO3TG. GPIO3 input rise/fall edge event trig\newline 10: GPIO4TG. GPIO4 input rise/fall edge event trig\newline 11: GPIO5TG. GPIO5 input rise/fall edge event trig\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{TIM0TGSRCR}
Address: 0x40001204. Reset: 0x00000000
\newline 
TIM0 trig select Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:4 & Reserve & RO & Reserve.\\ \hline
        3:0 & TGSRC & WR & tim0 trig select source.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{TIM1TGSRCR}
Address: 0x40001208. Reset: 0x00000000
\newline 
TIM1 trig select Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:4 & Reserve & RO & Reserve.\\ \hline
        3:0 & TGSRC & WR & tim1 trig select source.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{TIM2TGSRCR}
Address: 0x4000120C. Reset: 0x00000000
\newline 
TIM2 trig select Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:4 & Reserve & RO & Reserve.\\ \hline
        3:0 & TGSRC & WR & tim2 trig select source.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DBGER}
Address: 0x40001E00. Reset: 0x00000000
\newline 
Debug Enable Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & KEY & WO & DFT EN key. To write DBGEN, this field must be 0xA5.\\ \hline
        23:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & EN & WR & Only when KEY is matched and DBGLOCK LOCK(bit0) is 0, writing this bit is effective.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DBGLOCKR}
Address: 0x40001E04. Reset: 0x00000001
\newline 
DBG Lock Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & KEY & WO & DBG LOCK key. To write DBGLOCK, this field must be 0x5A.\\ \hline
        23:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & LOCK & WR & Only when KEY is matched, writing this bit is effective.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DBGMODE\_RES}
Address: 0x40001E08. Reset: 0x00000000
\newline 
DBG MODE register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:2 & Reserve & RO & Reserve.\\ \hline
        1:0 & MODE & WR & Select DBG mode, and start DBG test.\newline 0: NONE\newline 1: LEDDRV. LEDDRV debug test.\newline 2: ADC. ADC debug test.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DFTER\_RES}
Address: 0x40001F00. Reset: 0x00000000
\newline 
DFT Enable Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & KEY & WO & DFT EN key. To write DFTEN, this field must be 0xA5.\\ \hline
        23:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & EN & WR & Only when KEY is matched and DFTLOCK LOCK(bit0) is 0, writing this bit is effective.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DFTLOCKR\_RES}
Address: 0x40001F04. Reset: 0x00000001
\newline 
DFT Lock Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & KEY & WO & DFT LOCK key. To write DFTLOCK, this field must be 0x5A.\\ \hline
        23:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & LOCK & WR & Only when KEY is matched, writing this bit is effective.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DFTMODER\_RES}
Address: 0x40001F08. Reset: 0x00000000
\newline 
DFT MODE register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:4 & Reserve & RO & Reserve.\\ \hline
        3:0 & MODE & WR & Select DTF mode, and start DFT test.\newline 0x3: SCAN. Scan test.\newline 0x5: RAMBIST. Ram bist test.\newline 0xA: FLSBIST. Flash bist test.\\ \hline
		\end{xtabular}
	\end{center}

SYSCTRL address end \newline
GPIO address start \newline
\subsubsection{MODER}
Address: 0x400F0000. Reset: 0x0000A03F
\newline 
GPIO Mode Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:12 & Reserve & RO & Reserve.\\ \hline
        11:10 & MODE5 & WR & GPIO5 supports four modes, which can be\newline 0: INPUT\newline 1: OUTPUT\newline 2: ALTERNATE\newline 3: ANALOG\\ \hline
        9:8 & MODE4 & WR & GPIO4 supports four modes, which can be\newline 0: INPUT\newline 1: OUTPUT\newline 2: ALTERNATE\newline 3: ANALOG\\ \hline
        7:6 & MODE3 & WR & GPIO3 supports four modes, which can be\newline 0: INPUT\newline 1: OUTPUT\newline 2: ALTERNATE\newline 3: ANALOG\\ \hline
        5:4 & MODE2 & WR & GPIO2 supports four modes, which can be\newline 0: INPUT\newline 1: OUTPUT\newline 2: ALTERNATE\newline 3: ANALOG\\ \hline
        3:2 & MODE1 & WR & GPIO1 supports four modes, which can be\newline 0: INPUT\newline 1: OUTPUT\newline 2: Reserve\newline 3: ANALOG\\ \hline
        1:0 & MODE0 & WR & GPIO0 supports four modes, which can be\newline 0: INPUT\newline 1: OUTPUT\newline 2: Reserve\newline 3: ANALOG\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{STR}
Address: 0x400F0004. Reset: 0x00000000
\newline 
GPIO Strength Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:8 & Reserve & RO & Reserve.\\ \hline
        7:7 & ST7 & WR & GPIO7 strength configration\newline 0: OHM67. 67ohm. \newline 1: OHM57. 57ohm.\\ \hline
        6:6 & ST6 & WR & GPIO6 strength configration, as descripted in STR7.\\ \hline
        5:5 & ST5 & WR & GPIO5 strength configration, as descripted in STR7.\\ \hline
        4:4 & ST4 & WR & GPIO4 strength configration, as descripted in STR7.\\ \hline
        3:3 & ST3 & WR & GPIO3 strength configration, as descripted in STR7.\\ \hline
        2:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SLEWR}
Address: 0x400F0008. Reset: 0x00000000
\newline 
GPIO SLEW Rate Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:8 & Reserve & RO & Reserve.\\ \hline
        7:7 & RATE7 & WR & GPIO7 slew rate, which can be \newline 0: NS4. 4ns \newline 1: NS5. 5ns\\ \hline
        6:6 & RATE6 & WR & GPIO6 slew rate, which can be \newline 0: NS4. 4ns \newline 1: NS5. 5ns\\ \hline
        5:5 & RATE5 & WR & GPIO5 slew rate, which can be \newline 0: NS4. 4ns \newline 1: NS5. 5ns\\ \hline
        4:4 & RATE4 & WR & GPIO4 slew rate, which can be \newline 0: NS4. 4ns \newline 1: NS5. 5ns\\ \hline
        3:3 & RATE3 & WR & GPIO3 slew rate, which can be \newline 0: NS4. 4ns \newline 1: NS5. 5ns\\ \hline
        2:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{PUPDR}
Address: 0x400F000C. Reset: 0x00009540
\newline 
GPIO Pull-up/Pull-down Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:16 & Reserve & RO & Reserve.\\ \hline
        15:14 & PUPD7 & WR & GPIO7 Pull-up/Pull-down selection can be\newline 0: None\newline 1: PullUp\newline 2: PullDown\\ \hline
        13:12 & PUPD6 & WR & GPIO6 pull-up/pull-down selection can be\newline 0: None\newline 1: PullUp\newline 2: PullDown\\ \hline
        11:10 & PUPD5 & WR & GPIO5 pull-up/pull-down selection can be\newline 0: None\newline 1: PullUp\newline 2: PullDown\\ \hline
        9:8 & PUPD4 & WR & GPIO4 pull-up/pull-down selection can be\newline 0: None\newline 1: PullUp\newline 2: PullDown\\ \hline
        7:6 & PUPD3 & WR & GPIO3 pull-up/pull-down selection can be\newline 0: None\newline 1: PullUp\newline 2: PullDown\\ \hline
        5:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IDR}
Address: 0x400F0010. Reset: 0x000000FF
\newline 
GPIO Input Data Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:6 & Reserve & RO & Reserve.\\ \hline
        5:5 & ID5 & RO & If MODER5 is INPUT, this bit reflects the external voltage level on GPIO5.\\ \hline
        4:4 & ID4 & RO & If MODER4 is INPUT, this bit reflects the external voltage level on GPIO4.\\ \hline
        3:3 & ID3 & RO & If MODER3 is INPUT, this bit reflects the external voltage level on GPIO3.\\ \hline
        2:2 & ID2 & RO & If MODER2 is INPUT, this bit reflects the external voltage level on GPIO2.\\ \hline
        1:1 & ID1 & RO & If MODER1 is INPUT, this bit reflects the external voltage level on GPIO1.\\ \hline
        0:0 & ID0 & RO & If MODER0 is INPUT, this bit reflects the external voltage level on GPIO0.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{ODR}
Address: 0x400F0014. Reset: 0x00000000
\newline 
GPIO Output Data Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:6 & Reserve & RO & Reserve.\\ \hline
        5:5 & OD5 & WR & If MODER5 is OUTPUT, this bit sets the output voltage level of GPIO5.\\ \hline
        4:4 & OD4 & WR & If MODER4 is OUTPUT, this bit sets the output voltage level of GPIO4.\\ \hline
        3:3 & OD3 & WR & If MODER3 is OUTPUT, this bit sets the output voltage level of GPIO3.\\ \hline
        2:2 & OD2 & WR & If MODER2 is OUTPUT, this bit sets the output voltage level of GPIO2.\\ \hline
        1:1 & OD1 & WR & If MODER1 is OUTPUT this bit sets the output voltage level of GPIO1.\\ \hline
        0:0 & OD0 & WR & If MODER0 is OUTPUT, this bit sets the output voltage level of GPIO0.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{AFR}
Address: 0x400F0020. Reset: 0x00000000
\newline 
GPIO Alternate Function Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & Reserve & RO & Reserve.\\ \hline
        23:20 & AF5 & WR & Alternate selection for GPIO5, which can be\newline 0: Reserve0\newline 1: Reserve1\newline 2: Reserve2\newline 3: TIM\_OC\_CH1. This signal toggles at the monment of TIM0 count overflowing.\newline 4: PWM\_OC\_CH1. This signal toggles at the monment of LEDCTRL count overflowing.\newline 5: Reserve5\newline 6: Reserve6\newline 7: Reserve7\\ \hline
        19:16 & AF4 & WR & Alternate selection for GPIO4, which can be\newline 0: Reserve0\newline 1: LINCRX\_LINPHYTX. This signal can be LINC RX or LINS/LINM TX, depending on the TBD. \newline 2: LINCRX\_MONITOR. This signal reprensents LINC RX when TBD.\newline 3: TIM\_OC\_CH1. This signal toggles at the monment of TIM0 count overflowing.\newline 4: PWM\_OC\_CH1. This signal toggles at the monment of LEDCTRL count overflowing.\newline 5: Reserve5\newline 6: Reserve6\newline 7: Reserve7\\ \hline
        15:12 & AF3 & WR & Alternate selection for GPIO3, which can be\newline 0: RCC\_CLK. This signal can be system clock / 64 or slow 256KHz clock.\newline 1: LINCTX\_LINPHYRX. This signal can be LINC TX or LINS/LINM RX, depending on the TBD\newline 2: LINCTX\_MONITOR. This signal reprensents LINC TX when TBD.\newline 3: TIM\_OC\_CH0. This signal toggles at the monment of TIM0 count overflowing.\newline 4: PWM\_OC\_CH0. This signal toggles at the monment of LEDCTRL count overflowing.\newline 5: Reserve5\newline 6: Reserve6\newline 7: Reserve7\\ \hline
        11:8 & AF2 & WR & Alternate selection for GPIO2, which can be\newline 0: LEDCTRL\_CH2. This signal will be high, when LED2 current is turn on. This signal will be low, when LED2 current is turn off.\newline 1: RCC\_CLK. This signal can be system clock / 64 or slow 512KHz clock.\newline 2: Reserve2\newline 3: Reserve3\newline 4: Reserve4\newline 5: Reserve5\newline 6: Reserve6\newline 7: Reserve7\\ \hline
        7:4 & AF1 & WR & Alternate selection for GPIO1, which can be\newline 0: LEDCTRL\_CH1. This signal will be high, when LED1 current is turn on. This signal will be low, when LED1 current is turn off.\newline 1: Reserve1\newline 2: Reserve2\newline 3: Reserve3\newline 4: Reserve4\newline 5: Reserve5\newline 6: Reserve6\newline 7: Reserve7\\ \hline
        3:0 & AF0 & WR & Alternate  selection for GPIO0, which can be\newline 0: LEDCTRL\_CH0. This signal will be high, when LED0 current is turn on. This signal will be low, when LED0 current is turn off.\newline 1: Reserve1\newline 2: Reserve2\newline 3: Reserve3\newline 4: Reserve4\newline 5: Reserve5\newline 6: Reserve6\newline 7: Reserve7\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{EER}
Address: 0x400F002C. Reset: 0x00000000
\newline 
GPIO risr/fall edge enable Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:23 & Reserve & RO & Reserve.\\ \hline
        22:22 & FE5 & WR & Enable GPIO5 fall edge enable\newline 0: DIS. Disable detecting GPIO5 fall.\newline 1: EN. Enable detecting GPIO5 fall.\\ \hline
        21:21 & RE5 & WR & Enable GPIO5 rise edge enable\newline 0: DIS. Disable detecting GPIO5 rise.\newline 1: EN. Enable detecting GPIO5 rise.\\ \hline
        20:19 & Reserve & RO & Reserve.\\ \hline
        18:18 & FE4 & WR & Enable GPIO4 fall edge enable\newline 0: DIS. Disable detecting GPIO4 fall.\newline 1: EN. Enable detecting GPIO4 fall.\\ \hline
        17:17 & RE4 & WR & Enable GPIO4 rise edge enable\newline 0: DIS. Disable detecting GPIO4 rise.\newline 1: EN. Enable detecting GPIO4 rise.\\ \hline
        16:15 & Reserve & RO & Reserve.\\ \hline
        14:14 & FE3 & WR & Enable GPIO3 fall edge enable\newline 0: DIS. Disable detecting GPIO3 fall.\newline 1: EN. Enable detecting GPIO3 fall.\\ \hline
        13:13 & RE3 & WR & Enable gpio3 rise edge enable\newline 0: DIS. Disable detecting GPIO3 rise.\newline 1: EN. Enable detecting GPIO3 rise.\\ \hline
        12:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IER}
Address: 0x400F0030. Reset: 0x00000000
\newline 
GPIO Interrupt Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:23 & Reserve & RO & Reserve.\\ \hline
        22:22 & FI5 & WR & Enable GPIO5 fall edge interrupt\newline 0: DIS. Disable GPIO5 fall interrupt.\newline 1: EN. Enable GPIO5 fall interrupt.\\ \hline
        21:21 & RI5 & WR & Enable GPIO5 rise edge interrupt\newline 0: DIS. Disable GPIO5 rise interrupt.\newline 1: EN. Enable GPIO5 rise interrupt.\\ \hline
        20:19 & Reserve & RO & Reserve.\\ \hline
        18:18 & FI4 & WR & Enable GPIO4 fall edge interrupt\newline 0: DIS. Disable GPIO4 fall interrupt.\newline 1: EN. Enable GPIO4 fall interrupt.\\ \hline
        17:17 & RI4 & WR & Enable GPIO4 rise edge interrupt\newline 0: DIS. Disable GPIO4 rise interrupt.\newline 1: EN. Enable GPIO4 rise interrupt.\\ \hline
        16:15 & Reserve & RO & Reserve.\\ \hline
        14:14 & FI3 & WR & Enable GPIO3 fall edge interrupt\newline 0: DIS. Disable GPIO3 fall interrupt.\newline 1: EN. Enable GPIO3 fall interrupt.\\ \hline
        13:13 & RI3 & WR & Enable GPIO3 rise edge interrupt\newline 0: DIS. Disable GPIO3 rise interrupt.\newline 1: EN. Enable GPIO3 rise interrupt.\\ \hline
        12:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{ESR}
Address: 0x400F0034. Reset: 0x00000000
\newline 
GPIO Interrupt Status Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:23 & Reserve & RO & Reserve.\\ \hline
        22:22 & F5F & RO & GPIO5 fall edge flag\\ \hline
        21:21 & R5F & RO & GPIO5 rise edge flag\\ \hline
        20:19 & Reserve & RO & Reserve.\\ \hline
        18:18 & F4F & RO & GPIO4 fall edge flag\\ \hline
        17:17 & R4F & RO & GPIO4 rise edge flag\\ \hline
        16:15 & Reserve & RO & Reserve.\\ \hline
        14:14 & F3F & RO & GPIO3 fall edge flag\\ \hline
        13:13 & R3F & RO & GPIO3 rise edge flag\\ \hline
        12:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{ESCLR}
Address: 0x400F0038. Reset: 0x00000000
\newline 
GPIO Intterupt Status Clear Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:23 & Reserve & RO & Reserve.\\ \hline
        22:22 & F5CLR & WO & Writing 1 clear GPIO5 fall edge flag.\\ \hline
        21:21 & R5CLR & WO & Writing 1 clear GPIO5 rise edge flag.\\ \hline
        20:19 & Reserve & RO & Reserve.\\ \hline
        18:18 & F4CLR & WO & Writing 1 clear GPIO4 fall edge flag.\\ \hline
        17:17 & R4CLR & WO & Writing 1 clear GPIO4 rise edge flag.\\ \hline
        16:15 & Reserve & RO & Reserve.\\ \hline
        14:14 & F3CLR & WO & Writing 1 clear GPIO3 fall edge flag.\\ \hline
        13:13 & R3CLR & WO & Writing 1 clear GPIO3 rise edge flag.\\ \hline
        12:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

GPIO address end \newline
LIN address start \newline
\subsubsection{LINCR1}
Address: 0x4000A000. Reset: 0x00000082
\newline 
The LINCR1 register consists of control bits used to configure features of the LINFlexD. When accessing the LINCR1 register, each reserved bit should be written with its original reset value. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:17 & Reserve & RO & Reserve.\\ \hline
        16:16 & NLSE & WR & NLSE enables/disables capture of the LIN state (LINSR.LINS) whenever a bit error flag occurs (LINESR.BEF is set to 1).\newline 0: DIS. LINSR.LINS shows the current LIN state and does not capture the LIN state on bit error.\newline 1: EN. LINSR.LINS is captured when a bit error flag occurs.\\ \hline
        15:15 & CCD & WR & Checksum calculation disable.This bit disables the checksum calculation.\newline 0: DIS. Checksum calculation is done by hardware. The LINCFR register is read-only.\newline 1: EN. Checksum calculation is disabled. The LINCFR register is read/write. If the checksum field is enabled (CFD = 0), LINCFR can be programmed to send a software-calculated checksum/CRC.\\ \hline
        14:14 & CFD & WR & Checksum field disable.This bit disables the checksum field transmission.\newline 0: DIS. Checksum field is sent after the required number of data bytes are sent.\newline 1: EN. No checksum field is sent in the frame.\\ \hline
        13:13 & LASE & WR & Enables the autosynchronization, feature described in Automatic Resynchronization.\newline 0: DIS. Disable autosynchronization.\newline 1: EN. Enable autosynchronization.\\ \hline
        12:12 & AUTOWU & WR & Automatic Wake-Up Mode. This bit controls the behavior of the LINFlex hardware during Sleep mode.\newline 0: DIS. The SLEEP bit is cleared by software only.\newline 1: EN. The SLEEP bit is cleared by hardware whenever the LINSR.WUF bit is set.\\ \hline
        11:8 & MBL & WR & Controls the length of the break field generated in LIN master mode.\newline 0: B10. 10-bit break length\newline 1: B11. 11-bit break length\newline 2: B12. 12-bit break length\newline 3: B13. 13-bit break length\newline 4: B14. 14-bit break length\newline 5: B15. 15-bit break length\newline 6: B16. 16-bit break length\newline 7: B17. 17-bit break length\newline 8: B18. 18-bit break length\newline 9: B19. 19-bit break length\newline 10: B20. 20-bit break length\newline 11: B21. 21-bit break length\newline 12: B22. 22-bit break length\newline 13: B23. 23-bit break length\newline 14: B36. 36-bit break length\newline 15: B50. 50-bit break length\\ \hline
        7:7 & BF & WR & Controls the receive filter bypass function.\newline 0: DIS. Receiver ignores incoming frame if ID does not match any ID filter or if no ID filters are active.\newline 1: EN. If no ID filters are active, receiver responds to incoming frames. If ID filters are active, receiver responds if frame is received but does not match any filter.\\ \hline
        6:6 & Reserve & RO & Reserve.\\ \hline
        5:5 & LBKM & WR & Enables or disables Loop Back mode as described in Loop Back Mode.\newline 0: DIS. Disable Loop Back mode.\newline 1: EN. Enable Loop Back mode.\\ \hline
        4:4 & MME & WR & Master Mode Enable.\newline 0: SLAVE. Slave mode.\newline 1: MASTER. Master mode.\\ \hline
        3:3 & SSBL & WR & Sets the number of bit times for break field detection in slave mode.\newline 0: B11. 11-bit break length.\newline 1: B10. 10-bit break length.\\ \hline
        2:2 & RBLM & WR & Receive Buffer Locked Mode.\newline 0: DIS. Receiver is buffer is not locked. The next incoming message overwrites the previous one.\newline 1: EN. Receiver buffer is locked against overrun. Once the buffer is full, the next incoming message is discarded if the buffer is not released by software clearing the LINSR.RMB bit.\\ \hline
        1:1 & SLEEP & WR & Set by software to request LINFlexD to enter Sleep mode.   The SLEEP bit is cleared by software to exit sleep mode.  If LINCR1.AUTOWU and LINSR.WUF are set, SLEEP is automatically cleared by hardware to exit sleep mode.  SLEEP is effective in both LIN and UART modes.\\ \hline
        0:0 & INIT & WR & Set by software to switch the hardware into Initialization mode.   When software clears the INIT bit (and if the SLEEP bit is also 0), the LINFlexD enters Normal mode.  INIT is effective in both LIN and UART modes.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINIER}
Address: 0x4000A004. Reset: 0x00000000
\newline 
LIN interrupt enable register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:16 & Reserve & RO & Reserve.\\ \hline
        15:15 & SZIE & WR & Stuck at Zero Interrupt Enable\newline 0: DIS. Interrupt disabled.\newline 1: EN. Interrupt enabled. An interrupt is generated when the Stuck at Zero Flag (SZF) is set in LINESR or UARTSR.\\ \hline
        14:14 & OCIE & WR & Output Compare Interrupt Enable\newline 0: DIS. Interrupt disabled.\newline 1: EN. Interrupt enabled. An interrupt is generated when the Output Compare Flag (OCF) is set in LINESR or UARTSR.\\ \hline
        13:13 & BEIE & WR & Bit Error Interrupt Enable\newline 0: DIS. Interrupt disabled.\newline 1: EN. Interrupt enabled. An interrupt is generated when the Bit Error Flag (BEF) is set in LINESR.\\ \hline
        12:12 & CEIE & WR & Checksum Error Interrupt Enable\newline 0: DIS. Interrupt disabled.\newline 1: EN. Interrupt enabled. An interrupt is generated when the Checksum Error Flag (CEF) is set in LINESR.\\ \hline
        11:11 & HEIE & WR & Header Error Interrupt Enable\newline 0: DIS. Interrupt disabled.\newline 1: EN. Interrupt enabled. An interrupt is generated when the any of the following flags are set in LINESR: SFEF, SDEF, IDPEF.\\ \hline
        10:9 & Reserve & RO & Reserve.\\ \hline
        8:8 & FEIE & WR & Framing Error Interrupt Enable\newline 0: DIS. Interrupt disabled.\newline 1: EN. Interrupt enabled. An interrupt is generated when the Frame Error Flag (FEF) is set in LINESR or UARTSR.\\ \hline
        7:7 & BOIE & WR & Buffer Overrun Interrupt Enable\newline 0: DIS. Interrupt disabled.\newline 1: EN. Interrupt enabled. An interrupt is generated when the Buffer Overrun Flag (BOF) is set in LINESR or UARTSR.\\ \hline
        6:6 & LSIE & WR & LIN State Interrupt Enable\newline 0: DIS. Interrupt disabled.\newline 1: EN. Interrupt enabled. An interrupt generated on entering the following states: Sync Del, Sync Field, Identifier Field, Checksum.\\ \hline
        5:5 & WUIE & WR & Wake-up Interrupt Enable\newline 0: DIS. Interrupt disabled.\newline 1: EN. Interrupt enabled. An interrupt generated when the Wakeup Flag (WUF) is set in LINESR or UARTSR.\\ \hline
        4:4 & Reserve & RO & Reserve.\\ \hline
        3:3 & TOIE & WR & Timout Interrupt Enable\newline 0: DIS. Interrupt disabled.\newline 1: EN. Interrupt enabled. An interrupt generated when the LINFlexD is in UART mode and the Timeout bit (TO) is set in UARTSR.\\ \hline
        2:2 & DRIE & WR & Data Reception Complete Interrupt Enable\newline 0: DIS. Interrupt disabled.\newline 1: EN. Interrupt enabled. An interrupt generated when the Data Received Flag (DRF) is set in LINESR or UARTSR.\\ \hline
        1:1 & DTIE & WR & Data Transmitted Interrupt Enable\newline 0: DIS. Interrupt disabled.\newline 1: EN. Interrupt enabled. An interrupt generated when the Data Transmitted Flag (DTF) is set in LINESR or UARTSR.\\ \hline
        0:0 & HRIE & WR & Header Received Interrupt Enable\newline 0: DIS. Interrupt disabled.\newline 1: EN. Interrupt enabled. An interrupt is generated Header Received Flag (HRF) is set in LINSR.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINSR}
Address: 0x4000A008. Reset: 0x00000040
\newline 
The LINSR register contains status bits indicating the state of the LINFlexD hardware. Reset value of RDI reflects the LINFlexD_RX pin state. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:20 & Reserve & RO & Reserve.\\ \hline
        19:19 & AUTOSYNC\_COMP & WR & AUTOSYNC\_COMP is set when autosynchronization is enabled (LINCR1.LASE is set) and autosynchronization is complete. After AUTOSYNC\_COMP is set, the contents of LINIBRR and LINFBRR registers can be read.\\ \hline
        18:16 & RDC & RO & RDC contains the number of entries (bytes) in the receive data buffer in LIN mode.\newline 0: B1. 1 byte\newline 1: B2. 2 bytes\newline 2: B3. 3 bytes\newline 3: B4. 4 bytes\newline 4: B5. 5 bytes\newline 5: B6. 6 bytes\newline 6: B7. 7 bytes\newline 7: B8. 8 bytes\\ \hline
        15:12 & LINS & RO & LIN modes / normal mode states\\ \hline
        11:10 & Reserve & RO & Reserve.\\ \hline
        9:9 & RMB & WR & Release Message Buffer\newline 0: FREE. Buffer is free.\newline 1: READY. Buffer data is ready to be read by software. RMB should be cleared by software after reading the data received in the buffer.\\ \hline
        8:8 & DRBNE & WR & DRBNE is set by hardware as soon as the first byte of response is received and stored in DATA (when there is at least one data byte in reception buffer). Software should clear DRBNE after reading all the buffers.  DRBNE can be checked by software in the case of a response timeout event.  DRBNE is cleared by hardware in Initialization mode.\\ \hline
        7:7 & RXBUSY & RO & Receiver Busy Flag\newline 0: IDLE. Receiver is idle.\newline 1: BUSY. Reception is ongoing.\\ \hline
        6:6 & RDI & RO & Receive Data Input\\ \hline
        5:5 & WUF & WR & WUF is set by hardware when a falling edge is detected on the LINFlexD\_RX pin in either of the following conditions:   The LINFlexD is in slave mode and in Sleep mode.  The LINFlexD is in master mode is in either Sleep mode or Idle state.  WUF is cleared by hardware in Initialization mode.\\ \hline
        4:3 & Reserve & RO & Reserve.\\ \hline
        2:2 & DRF & WR & DRF is set by hardware and indicates that data reception has completed.  DRF is cleared by hardware in Initialization mode. DRF is not set when a framing error or checksum error occurs.\\ \hline
        1:1 & DTF & WR & DTF is set by hardware and indicates that data transmission has completed.  DTF is cleared by hardware in Initialization mode. DTF is not set in LIN mode when a bit error occurs and LINCR2.IOBE = 0.\\ \hline
        0:0 & HRF & WR & HRF is set by hardware when header reception completes and one of the following conditions is true.   All filters are inactive and LINCR1.BF = 1.  No match in any filter and LINCR1.BF = 1.  Tx filter match.  HRF is reset by hardware in Initialization mode and at end of completed or aborted frame.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINESR}
Address: 0x4000A00C. Reset: 0x00000000
\newline 
The LINESR register contains status bits for various error conditions. For detailed descriptions the error conditions. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:16 & Reserve & RO & Reserve.\\ \hline
        15:15 & SZF & WR & Set by hardware when a stuck-at-zero timeout error occurs.\\ \hline
        14:14 & OCF & WR & In master mode, OCF is set when counter LINTCSR.CNT matches the content of LINOCR.OC2.  In slave mode, OCF is set when the content of the counter LINTCSR.CNT matches the content of LINOCR.OC1 or LINOCR.OC2.  If OCF is set when LINTCSR.MODE = 0 and LINTCSR.IOT = 1, the LINFlexD goes to Idle state.  When LINTCSR.MODE = 0, OCF is cleared by hardware in Initialization mode.  When LINTCSR.MODE = 1, OCF maintains its status regardless of the LIN state.\\ \hline
        13:13 & BEF & WR & BEF is set by hardware when the LINFlexD detects a bit error.  BEF is cleared by hardware in Initialization mode.\\ \hline
        12:12 & CEF & WR & CEF is set by hardware when the received checksum does not match the hardware calculated checksum.  CEF is cleared by hardware in Initialization mode. CEF is never set if LINCR1.CCD or LINCR1.CFD is set.\\ \hline
        11:11 & SFEF & WR & SFEF is set by hardware when a sync field error occurs due to an inconsistent sync field.  SFEF is cleared by hardware in Initialization mode.\\ \hline
        10:10 & SDEF & WR & SDEF is set by hardware when a break delimiter error occurs because a break delimiter is too short (less than one bit time).  SDEF is cleared by hardware in Initialization mode.\\ \hline
        9:9 & IDPEF & WR & IDPEF is set by hardware LINFlexD detects an error in the ID parity.  IDPEF is cleared by hardware in Initialization mode.\\ \hline
        8:8 & FEF & WR & FEF is set by hardware when a framing error (invalid stop bit) occurs.  FEF is cleared by hardware in Initialization mode.\\ \hline
        7:7 & BOF & WR & BOF is set by hardware when a new byte is received and LINSR.RMB bit is not cleared.  BOF is cleared by hardware in Initialization mode.\\ \hline
        6:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & NF & WR & NF is set by hardware when noise is detected in a receive character.  NF is cleared by hardware in Initialization mode.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{UARTCR}
Address: 0x4000A010. Reset: 0x00000000
\newline 
The UARTCR register contains control bits for UART mode. Always write 0 to reserved bits when writing to UARTCR. In UART mode, the LINFlexD does not support communication with Special Word Length (UARTCR.WLS = 1) in buffer mode. In UART mode, the LINFlexD supports communication with Special Word Length (UARTCR.WLS = 1) in FIFO mode only with UARTCR.WL[1:0] = 11. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:31 & MIS & WR & Monitor Idle State\newline 0: DIS. UARTCTO monitors the number of bits to be received.\newline 1: EN. UARTCTO monitors the idle state of the reception line.\\ \hline
        30:28 & CSP & WR & The CSP bits select the sample point during reduced oversampling.  CSP can have the following range of values for the specified oversampling rate:\\ \hline
        27:24 & OSR & WR & Selects the number of samples taken for a bit when reduced oversampling is enabled.  The values allowed for OSR are 4, 5, 6, and 8. When idle state monitoring is enabled (MIS = 1), the allowed OSR values are 4 and 8. OSR can be read in any mode, but can be written only during Initialization mode.\\ \hline
        23:23 & ROSE & WR & Reduced Oversampling Enable.\newline 0: DIS. Each bit is oversampled sixteen times.\newline 1: EN. OSR bits determine the oversampling rate.\\ \hline
        22:20 & NEF & WR & The NEF bits set the number of expected frames in UART reception mode. If the DTU bit is set, then the UART timeout counter is reset after the configured number of frames have been received.   NEF can be read in any mode, but can be written only during Initialization mode.\\ \hline
        19:19 & DTU & WR & Disable Timeout in UART mode\newline 0: EN. Timeout must be handled by software.\newline 1: DIS. Timeout in UART mode is disabled after the configured number of data frames are received.\\ \hline
        18:17 & SBUR & WR & Number of Stop Bits in UART Reception Mode\newline 0: SP1. 1 stop bit\newline 1: SP2. 2 stop bits\newline 2: SP3. 3 stop bits\\ \hline
        16:16 & WLS & WR & Special Word Length in UART Mode.\newline 0: DIS. Disable 12-bit + parity bit in reception.\newline 1: EN. Enable 12-bit + parity bit in reception (UART mode).\\ \hline
        15:13 & TDFL\_TFC & WR & The TDFL\_TFC field has one of two functions depending on the mode of operation. UART Buffer Mode:  When the LINFlexD is in UART buffer mode (TFBM = 0), TDFL\_TFC is read/write and defines the number of bytes to be transmitted.   x00:  1 byte  x01:  2 bytes  x10:  3 bytes  x11:  4 bytes  The first bit is reserved and not implemented.   When the UART data length is configured as half-word (WL = 10 or 11), the only valid values for TDFL\_TFC are x01 and x11. UART FIFO Mode:  When the LINFlexD is in UART FIFO mode (TFBM = 1), TDFL\_TFC is read-only and contains the number of entries (bytes) in the Tx FIFO.   000:  Empty  001:  1 byte  010:  2 bytes  011:  3 bytes  100:  4 bytes  All other values: Reserved  TDFL\_TFC can be read in any mode, but can be written only during Initialization mode, when the UART bit is set.\\ \hline
        12:10 & RDFL\_RFC & WR & The RDFL\_RFC field has one of two functions depending on the mode of operation. UART Buffer Mode:  When the LINFlexD is in UART buffer mode (RFBM = 0), RDFL\_RFC is read/write and defines the number of bytes to be received:   x00:  1 byte  x01:  2 bytes  x10:  3 bytes  x11:  4 bytes  The first bit is reserved and not implemented.   When the UART data length is configured as half-word (WL = 10 or 11), the only valid values for RDFL\_RFC are x01 and x11.  RDFL\_RFC should be programmed to be greater than or equal to NEF (number of expected frames). UART FIFO Mode:  When the LINFlexD is in UART FIFO mode (RFBM = 1), RDFL\_RFC is read-only and contains the number of entries (bytes) in the Rx FIFO:   000:  Empty  001:  1 byte  010:  2 bytes (1.5 byte if WLS = 1)  011:  3 bytes  100:  4 bytes (2x1.5 bytes if WLS = 1)  All other values: Reserved  RDFL\_RFC can be read in any mode, but can be written only during Initialization mode, when the UART bit is set.\\ \hline
        9:9 & RFBM & WR & Rx FIFO/Buffer Mode\newline 0: DIS. Rx buffer mode enabled.\newline 1: EN. Rx FIFO mode enabled.\\ \hline
        8:8 & TFBM & WR & Tx FIFO/Buffer Mode\newline 0: MODE\_BUF. Tx buffer mode enabled.\newline 1: MODE\_FIFO. Tx FIFO mode enabled.\\ \hline
        7:7 & WL1 & WR & Word Length in UART Mode\\ \hline
        6:6 & PC1 & WR & Parity Control\\ \hline
        5:5 & RXEN & WR & Receive Enable\newline 0: DIS. Receiver disabled.\newline 1: EN. Receiver enabled.\\ \hline
        4:4 & TXEN & WR & Transmitter Enable\newline 0: DIS. Transmitter disabled.\newline 1: EN. Transmitter enabled.\\ \hline
        3:3 & PC0 & WR & Parity Control;\newline even,                  when PC1 = 0, PC0 = 0;\newline odd,                   when PC1 = 0, PC0 = 1;\newline logic0,                when PC1 = 1, PC0 = 0;\newline logic1,                when PC1 = 1, PC0 = 1;\\ \hline
        2:2 & PCE & WR & Parity Control Enable\newline 0: DIS. Parity transmit/check disabled.\newline 1: EN. Parity transmit/check enabled.\\ \hline
        1:1 & WL0 & WR & Word Length in UART Mode.\newline 7bits data + parity,  when WL1 = 0, WL0 = 0;\newline 8bits data,           when WL1 = 0, WL0 = 1, PCE = 0;\newline 8bits data + parity,  when WL1 = 0, WL0 = 1, PCE = 1;\newline 15bits data + parity, when WL1 = 1, WL0 = 0;\newline 16bits data,          when WL1 = 1, WL0 = 1, PCE = 0;\newline 16bits data + parity, when WL1 = 1, WL0 = 1, PCE = 1;\\ \hline
        0:0 & UART & WR & UART Mode Enable\newline 0: MODE\_LIN. LIN mode\newline 1: MODE\_UART. UART mode\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{UARTSR}
Address: 0x4000A014. Reset: 0x00000000
\newline 
The UARTSR register contains status bits for UART mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:16 & Reserve & RO & Reserve.\\ \hline
        15:15 & SZF & WR & SZF is set by hardware when 100 dominant bits are detected. An interrupt is generated if LINIER.SZIE = 1.  SZF reflects the same value as LINESR.SZF when the LINFlexD is not in Initialization mode and UARTCR.UART = 1.\\ \hline
        14:14 & OCF & WR & OCF Output Compare Flag\newline 0: INACTIVE. No output compare event occurred.\newline 1: ACTIVE. The content of the timeout counter matched the content of LINOCR.\\ \hline
        13:10 & PE & WR & Indicates parity error in corresponding receive data byte.\newline 0: INACTIVE. No parity error detected.\newline 1: ACTIVE. Parity error detected.\\ \hline
        9:9 & RMB & WR & Release Message Buffer\newline 0: FREE. Buffer is free.\newline 1: RDY. Buffer data is ready to be read by software.\\ \hline
        8:8 & FEF & WR & FEF is set by hardware when the LINFlexD detects a framing error (invalid stop bit). An interrupt is generated if LINIER.FEIE = 1.   FEF reflects the same value as LINESR.FEF when the LINFlexD is not in Initialization mode and UARTCR.UART = 1.\\ \hline
        7:7 & BOF & WR & In UART buffer mode, BOF is set by hardware when there is a new byte received and the RMB bit is not cleared. If LINCR.RBLM = 1, the newly received message is discarded. If LINCR.RBLM = 0, the newly received message overwrites the buffer.   In UART FIFO mode, BOF is set when there is a new byte received and the Rx FIFO is full. In UART FIFO mode, once Rx FIFO is full, the new received message is discarded regardless of the value of the RBLM bit.  When BOF is set, an interrupt is generated if LINIER.BOIE = 1.   BOF reflects the same value as LINESR.BOF when the LINFlexD is not in Initialization mode and UARTCR.UART = 0.\\ \hline
        6:6 & RDI & RO & Reflects the current state of the LINFlexD\_RX pin when UARTCR.UART = 1\\ \hline
        5:5 & WUF & WR & WUF is set by hardware when a falling edge is detected on the LINFlexD\_RX pin in Sleep mode. An interrupt is generated if LINIER.WUIE = 1.  WUF reflects the same value as LINSR.WUF when the LINFlexD is not in Initialization mode and UARTCR.UART = 1.\\ \hline
        4:4 & RFNE & RO & RFNE is set by hardware in UART FIFO mode (RFBM = 1), when there is at least one data byte present in the receive FIFO. RFNE is a read-only bit for debugging purposes.  RFNE can be used by software in case of a timeout event.\\ \hline
        3:3 & TO & WR & TO is set by hardware when a UART timeout occurs - in other words, the value of UARTCTO becomes equal to the preset value of the timeout . An interrupt is generated if LINIER.TOIE equals to 1.  The GCR.SR bit should be used to reset the receiver FSM to the Idle state in the event of timeout for UART reception in both UART buffer and UART FIFO modes.\\ \hline
        2:2 & DRF\_RFE & WR & The DRF\_RFE bit function depends on whether the LINFlexD is operating in UART buffer mode or UART FIFO mode. UART Buffer Mode:  In UART buffer mode (RFBM = 0), the DRF (data received flag) function of DRF\_RFE is used. DRF is set by hardware in UART buffer mode when the number of bytes programmed in UARTCR.RDFL are received. An interrupt is generated if LINIER.DRIE = 1.  DRF is set when the configured number of valid stop bits are received for the last frame.  DRF is set regardless of parity error, overrun error, or framing error if the framing error is in the last STOP bit configured.  DRF reflects the same value as LINSR.DRF when the LINFlexD is not in Initialization mode and UARTCR.UART = 1.  DRF can be read/cleared by software. Writing 1 clears DRF.  UART FIFO Mode:  In UART FIFO mode (RFBM = 1), the RFE (Rx FIFO empty) function of DRF\_RFE is used. RFE is set by hardware in UART FIFO mode when the Rx FIFO is empty.   RFE is a read-only bit for debugging purposes. It is internally used by the DMA Rx interface.\\ \hline
        1:1 & DTF\_TFF & WR & The DTF\_TFF bit function depends on whether the LINFlexD is operating in UART buffer mode or UART FIFO mode.  UART Buffer Mode:  In UART buffer mode (RFBM = 0), the DTF (data transmitted flag) function of DTF\_TFF is used. DTF is set by hardware in UART buffer mode when data transmission completes. An interrupt is generated if LINIER.DTIE = 1.  DTF reflects the same value as LINSR.DTF when the LINFlexD is not in Initialization mode and UARTCR.UART = 1.  DTF can be read/cleared by software. Writing 1 clears DTF.  UART FIFO Mode:  In UART FIFO mode (RFBM = 1), the TFF (Tx FIFO full) function of DTF\_TFF is used. TFF is set by hardware in UART FIFO mode when Tx FIFO is full.   TFF is a read-only bit for debugging purposes. It is internally used by the DMA Tx interface.\\ \hline
        0:0 & NF & WR & Set by hardware when noise is detected in the received character.  NF reflects the same value as LINESR.NF when the LINFlexD is not in Initialization mode and the UARTCR.UART = 1.   During reduced oversampling (UARTCR.ROSE = 1), the NF bit is enabled only when UARTCR.OSR = 8.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINTCSR}
Address: 0x4000A018. Reset: 0x00000200
\newline 
The LINTCSR register contains control and status bits for the LIN timeout feature. When LINTCSR.MODE = 0, any activity on the transmit or receive pins will cause an unwanted change in the value of the 8-bit field Output Compare Value 2 (OC2) of the LIN Output Compare register (LINOCR). If the LINFlexD is enabled in LIN mode and the value of LINTCSR.MODE is changed from 1 to 0, the old values of LINOCR.OC1 and LINOCR.OC2 are retained. As a consequence, if the LINFlexD is reconfigured from UART mode to LIN mode, or LINTCSR.MODE is changed from 1 to 0, an incorrect timeout exception is generated when a LIN communication starts. To avoid this, set LINTCSR.MODE to 1, reconfigure the LINFlexD in LIN mode, then reset LINTCSR.MODE to 0. Before switching LINTCSR.MODE from 1 to 0 between frames, load LINOCR with 0xFFFF. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:11 & Reserve & RO & Reserve.\\ \hline
        10:10 & MODE & WR & LIN timeout mode\newline 0: MODE\_LIN. LIN mode\newline 1: MODE\_OC. Output compare mode\\ \hline
        9:9 & IOT & WR & Idle on Timeout\newline 0: DIS. LIN state machine does not reset to Idle on timeout.\newline 1: EN. LIN state machine resets to Idle on timeout event.\\ \hline
        8:8 & TOCE & WR & Timeout Conuter Enable\newline 0: DIS. Timeout counter disabled. UARTSR.OCF flag is not set on an output compare event.\newline 1: EN. Timeout counter enabled. UARTSR.OCF is set if an output compare event occurs.\\ \hline
        7:0 & CNT & RO & The value of the timeout counter. For proper functionality of this counter, LINIBRR should be greater than or equal to 5.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINOCR}
Address: 0x4000A01C. Reset: 0x0000FFFF
\newline 
The LINOCR register contains the value to be compared to the LINTCSR.CNT value.  LINOCR is writable by software only in when the counter is in output compare mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:16 & Reserve & RO & Reserve.\\ \hline
        15:8 & OC2 & WR & Output compare value 2.\\ \hline
        7:0 & OC1 & WR & Output compare value 1.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINTOCR}
Address: 0x4000A020. Reset: 0x00000E2C
\newline 
The LINTOCR register contains the LIN mode response and header timeout values. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:12 & Reserve & RO & Reserve.\\ \hline
        11:8 & RTO & WR & Response Timeout Value - The response timeout duration(in bit time for 1 byte).\\ \hline
        7:7 & Reserve & RO & Reserve.\\ \hline
        6:0 & HTO & WR & HTO specifies the header timeout duration (in bit time). HTO can be written only for slave mode. The header timeout should be programmed without considering 11 bits of break field.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINFBRR}
Address: 0x4000A024. Reset: 0x00000000
\newline 
LINFBRR sets the fractional part of the LIN baud rate. When LINCR1.LASE = 1, LINFBRR should be read only after LINSR.AUTOSYNC_COMP is set to obtain the correct value. LINFBRR cannot be used when reduced oversampling is enabled (UARTCR.ROSE = 1). 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:4 & Reserve & RO & Reserve.\\ \hline
        3:0 & FBR & WR & Fractional Baud Rate.\newline 0: DIV0\_16. Fraction(LDIV) = 0\newline 1: DIV1\_16. Fraction(LDIV) = 1/16\newline 2: DIV2\_16. Fraction(LDIV) = 2/16\newline 3: DIV3\_16. Fraction(LDIV) = 3/16\newline 4: DIV4\_16. Fraction(LDIV) = 4/16\newline 5: DIV5\_16. Fraction(LDIV) = 5/16\newline 6: DIV6\_16. Fraction(LDIV) = 6/16\newline 7: DIV7\_16. Fraction(LDIV) = 7/16\newline 8: DIV8\_16. Fraction(LDIV) = 8/16\newline 9: DIV9\_16. Fraction(LDIV) = 9/16\newline 10: DIV10\_16. Fraction(LDIV) = 10/16\newline 11: DIV11\_16. Fraction(LDIV) = 11/16\newline 12: DIV12\_16. Fraction(LDIV) = 12/16\newline 13: DIV13\_16. Fraction(LDIV) = 13/16\newline 14: DIV14\_16. Fraction(LDIV) = 14/16\newline 15: DIV15\_16. Fraction(LDIV) = 15/16\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINIBRR}
Address: 0x4000A028. Reset: 0x00000000
\newline 
LINIBRR sets the integer part of the LIN baud rate. When LINCR1.LASE = 1, LINIBRR should be read only after LINSR.AUTOSYNC_COMP is set to obtain the correct value. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:20 & Reserve & RO & Reserve.\\ \hline
        19:0 & IBR & WR & The IBR bits, along with the fractional baud rate bits in LINFBRR, set the LIN baud rate.   IBR = 0x0:  LIN clock disabled  IBR = 0x1:  Mantissa(LDIV) = 1  ...  IBR = 0xFFFFE:  Mantissa(LDIV) = 1048574  IBR = 0xFFFFF:  Mantissa(LDIV) = 1048575  IBR can be read in any mode, but can be written only during Initialization mode.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINCFR}
Address: 0x4000A02C. Reset: 0x00000000
\newline 
There is a delay between 4 to 6 clock cycles of bus clock for the internal checksums value (which is clocked with ipg_baud_clk/16 * LDIV) to reflect on LINCFR. Due to synchronization structures between the two input clocks to the LINFlexD, the write to this register is delayed between 2 to 3 clock cycles of bus clock. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:8 & Reserve & RO & Reserve.\\ \hline
        7:0 & CF & WR & When LINCR1.CCD = 0, the CF bits are read-only and are calculated by hardware.   When LINCR1.CCD = 1, the CF bits can be written by software.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINCR2}
Address: 0x4000A030. Reset: 0x00006000
\newline 
The LINCR2 register contains control and status bits related to buffer operations. When accessing LINCR2, each reserved bit should be written with its original reset value. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:16 & Reserve & RO & Reserve.\\ \hline
        15:15 & TBDE & WR & Two-Bit Delimiter Enable.\newline 0: DIS. Delimiter length in break field is 1 bit.\newline 1: EN. Delimiter length in break field is 2 bits.\\ \hline
        14:14 & IOBE & WR & Idle on Bit Error\newline 0: DIS. Bit error does not reset LIN state machine.\newline 1: EN. Bit error resets LIN state machine.\\ \hline
        13:13 & IOPE & WR & Idle on Identifier Parity Error\newline 0: DIS. Parity error does not reset LIN state machine.\newline 1: EN. Parity error resets LIN state machine.\\ \hline
        12:12 & WURQ & WR & Setting WURQ generates a wakeup request. The character sent during wakeup is copied from DATA0. WURQ is reset by hardware when the wakeup character has been transmitted.   WURQ cannot be set in Sleep mode. Software must exit Sleep mode before setting WURQ.   Bit error is not checked when transmitting the wakeup request.\\ \hline
        11:11 & DDRQ & WR & DDRQ is set by software to stop data reception if the frame does not concern the node. DDRQ is reset by hardware once the LINFlexD ignores the response and moves to Idle state.   For a LIN slave, DDRQ can be set only when LINSR.HRF = 1 and the identifier is software-filtered.\\ \hline
        10:10 & DTRQ & WR & DTRQ is set by software in slave mode to request the transmission of the LIN data field stored in the buffer data register. DTRQ can be set only when LINSR.HRF = 1 (to ensure that data transmission is requested only after a header reception).   DTRQ is cleared by hardware when the request has been completed, or on abort request or error condition.   In master mode, DTRQ is set by hardware when BIDR.DIR = 1 and header transmission is complete.\\ \hline
        9:9 & ABRQ & WR & ABRQ is set by software to abort the current transmission. The LINFlexD aborts the transmission at the end of the current bit.   ABRQ is cleared by hardware when the transmission has been aborted.  ABRQ can abort a wakeup request and can also be used in UART mode.\\ \hline
        8:8 & HTRQ & WR & HTRQ is set by software to request the transmission of a LIN header.   HTRQ is cleared by hardware when the request has been completed or on abort request.   HTRQ has no effect in UART mode. In master mode, if both HTRQ and ABRQ are set at the same time then ABRQ has no effect. Similarly, in slave mode after header reception, if DTRQ and ABRQ are simultaneously set then ABRQ has no effect.\\ \hline
        7:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{BIDR}
Address: 0x4000A034. Reset: 0x00000000
\newline 
The BIDR register contains bits that provide information about the identifier of the transaction and other related information. All the fields (ID, CSS, DIR, DFL) of the BIDR register must be updated when an ID filter (enabled) in Slave mode (Tx or Rx) matches the ID received. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:17 & Reserve & RO & Reserve.\\ \hline
        16:16 & CCS\_A & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        15:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame.   DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copies it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA registers.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.   The ID field can be written only in master mode (LINCR1.MME = 1).\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{BDRL}
Address: 0x4000A038. Reset: 0x00000000
\newline 
Bytes 0-3 of the 8 byte data buffer. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & DATA3 & WR & data3.\\ \hline
        23:16 & DATA2 & WR & data2.\\ \hline
        15:8 & DATA1 & WR & data1.\\ \hline
        7:0 & DATA0 & WR & data0.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{BDRM}
Address: 0x4000A03C. Reset: 0x00000000
\newline 
Bytes 4-7 of the 8 byte data buffer. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & DATA7 & WR & data7.\\ \hline
        23:16 & DATA6 & WR & data6.\\ \hline
        15:8 & DATA5 & WR & data5.\\ \hline
        7:0 & DATA4 & WR & data4.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFER}
Address: 0x4000A040. Reset: 0x00000000
\newline 
The IFER register enables/disables the identifier filters. There is one filter active (FACT) bit for each filter. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:16 & Reserve & RO & Reserve.\\ \hline
        15:0 & FACT & WR & One bit for each identifier filter.  Software sets FACT[n] to activate the filter n in identifier list mode.  In identifier mask mode, FACT[2n+1] have no effect on the corresponding filters as they act as mask for identifier 2n.   FACT[n] can be read in any mode, but can be written only during Initialization mode.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFMI}
Address: 0x4000A044. Reset: 0x00000000
\newline 
The IFMI register contains the index corresponding to the received identifier. It can be used to read or write the data directly in RAM. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:5 & Reserve & RO & Reserve.\\ \hline
        4:0 & IFMI & RO & Contains the index corresponding to the received identifier.   Upon a filter match with filter x, IFMI[N:0] = x+1.  On no match, IFMI is equal to 0x00.  IFMI can be used to directly write or read the data in RAM.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFMR}
Address: 0x4000A048. Reset: 0x00000000
\newline 
The IFMR register configures the modes of filters. There is one IFM bit for each pair of filters. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:8 & Reserve & RO & Reserve.\\ \hline
        7:0 & IFM & WR & 0:  Filters 2n and 2n+1 are in identifier list mode.  1:  Filters 2n and 2n+1 are in mask mode. Filter 2n+1 is the mask for filter 2n.  IFM[n] can be read in any mode, but can be written only during Initialization mode.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR0}
Address: 0x4000A04C. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR1}
Address: 0x4000A050. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR2}
Address: 0x4000A054. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR3}
Address: 0x4000A058. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR4}
Address: 0x4000A05C. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR5}
Address: 0x4000A060. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR6}
Address: 0x4000A064. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR7}
Address: 0x4000A068. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR8}
Address: 0x4000A06C. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR9}
Address: 0x4000A070. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR10}
Address: 0x4000A074. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR11}
Address: 0x4000A078. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR12}
Address: 0x4000A07C. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR13}
Address: 0x4000A080. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR14}
Address: 0x4000A084. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR15}
Address: 0x4000A088. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR0}
Address: 0x4000A04C. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR1}
Address: 0x4000A050. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR2}
Address: 0x4000A054. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR3}
Address: 0x4000A058. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR4}
Address: 0x4000A05C. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR5}
Address: 0x4000A060. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR6}
Address: 0x4000A064. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR7}
Address: 0x4000A068. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR8}
Address: 0x4000A06C. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR9}
Address: 0x4000A070. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR10}
Address: 0x4000A074. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR11}
Address: 0x4000A078. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR12}
Address: 0x4000A07C. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR13}
Address: 0x4000A080. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR14}
Address: 0x4000A084. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFCR15}
Address: 0x4000A088. Reset: 0x00000000
\newline 
There is an Identifier Filter Control Register (IFCRn) for each filter. The IFCRn registers are read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:10 & DFL & WR & Number of data bytes in the response part of the frame. \newline DFL = Number of data bytes - 1.\\ \hline
        9:9 & DIR & WR & Controls the direction of the data field.\newline 0: RECV. LINFlexD receives the data and copy it to the DATA registers.\newline 1: TRANS. LINFlexD transmits the data from the DATA register.\\ \hline
        8:8 & CCS & WR & Controls the type of checksum applied on the current message.\newline 0: ENHANCE. Enhanced checksum covering identifier and data fields. This is compatible with LIN specification rev. 2.0 and higher.\newline 1: CLASSIC. Classic checksum covering data field only. This is compatible with LIN specification rev. 1.3 and lower.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & ID & WR & Identifier part of the identifier field without the identifier parity.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{GCR}
Address: 0x4000A08C. Reset: 0x00000000
\newline 
The GCR register contains control bits that apply to both LIN and UART modes.  The GCR register is read-only in Normal mode and can be written only in Initialization mode. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:6 & Reserve & RO & Reserve.\\ \hline
        5:5 & TDFBM & WR & Controls whether the first bit of transmit data (payload only) is the most or least significant bit from the respective buffer data register.\newline 0: LSB. The first bit of transmitted data is the least significant bit of the buffer data register (DATA0[0], DATA1[0], DATA2[0], DATA3[0], DATA4[0], DATA5[0], DATA6[0], DATA7[0]).\newline 1: MSB. The first bit of transmitted data is the most significant bit of the buffer data register (DATA0[7], DATA1[7], DATA2[7], DATA3[7], DATA4[7], DATA5[7], DATA6[7], DATA7[7]).\\ \hline
        4:4 & RDFBM & WR & Controls whether the first bit of received data (payload only) is mapped to the most or least significant bit from the respective buffer data register.\newline 0: LSB. The first bit of received data is mapped to least significant bit of the buffer data register (DATA0[0], DATA1[0], DATA2[0], DATA3[0], DATA4[0], DATA5[0], DATA6[0], DATA7[0]).\newline 1: MSB. The first bit of received data is mapped to the most significant bit of the buffer data register (DATA0[7], DATA1[7], DATA2[7], DATA3[7], DATA4[7], DATA5[7], DATA6[7], DATA7[7]).\\ \hline
        3:3 & TDLIS & WR & Controls the data inversion of transmitted data (payload only).\newline 0: NO\_INV. Transmitted data is not inverted.\newline 1: INV. Transmitted data is inverted.\\ \hline
        2:2 & RDLIS & WR & Controls the data inversion of received data (payload only).\newline 0: NO\_INV. Received data is not inverted.\newline 1: INV. Received data is inverted.\\ \hline
        1:1 & STOP & WR & Controls the number of stop bits transmitted for all fields (delimiter, sync, ID, checksum, payload).\newline 0: SP1. One stop bit.\newline 1: SP2. Two stop bits.\\ \hline
        0:0 & SR & WR & Writing 1 to SR executes a soft reset of the LINFlexD (FSMs, FIFO pointers, counters, timers, status and error registers) without modifying the configuration registers. SR should be cleared by software to perform further operations (SR is not cleared by hardware).   The SR bit can be written only be software in Initialization mode. The read value of SR is always 0.   When writing 1 to SR, below register fields are reset:\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{UARTPTO}
Address: 0x4000A090. Reset: 0x00000FFF
\newline 
The UARTPTO register contains the preset value of the timeout register in UART mode and is programmed according to the number of bits to be received or to monitor the idle state of the reception line. The UARTPTO register can be written by software at any time. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:12 & Reserve & RO & Reserve.\\ \hline
        11:0 & PTO & WR & PTO defines the preset value of timeout counter. A zero value is forbidden; otherwise, the UARTSR[TO] status bit is immediately set.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{UARTCTO}
Address: 0x4000A094. Reset: 0x00000000
\newline 
The UARTCTO register contains the current timeout value in UART mode. UARTCTO is used with the UARTPTO register to monitor the number of bits received by UART or to monitor the idle state of the reception line.   UART timeout works in both CPU and DMA modes.  The timeout counter:   Starts at zero and counts upward.  Is clocked with ipg_baud_clk / (16 * LDIV) synchronized to bus clock (when UARTCR.ROSE = 0).  Is clocked with ipg_baud_clk / (UARTCR.OSR * LINIBRR.IBR) synchronized to bus clock (when UARTCR.ROSE = 1).  Is automatically enabled when UARTCR.RXEN = 1.  Due to synchronization, there is a delay between 4 to 6 clock cycles of bus clock for the internal value (which is clocked with ipg_baud_clk/16 * LDIV) to reflect on UARTCTO.  The timeout counter is reset when one of the following conditions occurs:   The number of frames received is equal to UARTCR.NEF.  UARTCTO becomes equal to UARTPTO.  UARTPTO is written.  UARTSR.DRF is set and UARTCR.DTU = 1.  
ewpage 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:12 & Reserve & RO & Reserve.\\ \hline
        11:0 & CTO & RO & CTO defines the current value of the timeout counter. CTO is a read-only field. CTO is reset every time UARTPTO is written, or UARTCTO = UARTPTO, or by hard/soft reset. When the CTO value matches the preset value (UARTPTO.PTO), the status bit UARTSR.TO is set.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINOUTPHY}
Address: 0x4000A100. Reset: 0x00000306
\newline 
LINOUT Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:10 & Reserve & RO & Reserve.\\ \hline
        9:8 & STR & WR & TX short current control.\\ \hline
        7:4 & SLOPE\_SEL & WR & TX recessive to dominant slope control.\\ \hline
        3:3 & SLOPE\_ENHANCE & WR & lin slope enhance. \newline 0: OFF. slope enhance disable.\newline 1: ON. slope enhance enable.\\ \hline
        2:2 & TXPU & WR & TX pull-up enable. \newline 0: DIS. TX PULL up disable.\newline 1: EN. TX PULL up enable.\\ \hline
        1:1 & RXEN & WR & Enable LIN rx. \newline 0: DIS. RX disable.\newline 1: EN. RX enable.\\ \hline
        0:0 & TXEN & WR & Enable LIN Tx. \newline 0: DIS. TX disable.\newline 1: EN. TX enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LININPHY}
Address: 0x4000A104. Reset: 0x00000186
\newline 
LININ Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:10 & Reserve & RO & Reserve.\\ \hline
        9:8 & STR & WR & TX short current control.\\ \hline
        7:4 & SLOPE\_SEL & WR & TX recessive to dominant slope control.\\ \hline
        3:3 & SLOPE\_ENHANCE & WR & lin slope enhance. \newline 0: OFF. slope enhance disable.\newline 1: ON. slope enhance enable.\\ \hline
        2:2 & TXPU & WR & TX pull-up enable. \newline 0: DIS. TX PULL up disable.\newline 1: EN. TX PULL up enable.\\ \hline
        1:1 & RXEN & WR & Enable LIN rx. \newline 0: DIS. RX disable.\newline 1: EN. RX enable.\\ \hline
        0:0 & TXEN & WR & Enable LIN Tx. \newline 0: DIS. TX disable.\newline 1: EN. TX enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINSWITCH}
Address: 0x4000A108. Reset: 0x00000001
\newline 
LIN SWITCH Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & EN & WR & LINS connects with LINM.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINTESTMODE}
Address: 0x4000A10C. Reset: 0x00000000
\newline 
LIN MODE Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & KEY & WO & Only when KEY is 0xA5, write bit 0-4 is effective.\\ \hline
        23:5 & Reserve & RO & Reserve.\\ \hline
        4:4 & switch\_monitor\_en & WR & when linc connects with linsphy, this bit control whether monitor tx, rx by pad. \newline 0: DISABLE. monitor disable.\newline 1: ENABLE. monitor enable.\\ \hline
        3:3 & switch\_linc\_slave & WR & lin controler connected with lins phy or linm phy. \newline 0: LINSPHY. lin controler connected with lins phy.\newline 1: LINMPHY. lin controler connected with linm phy.\\ \hline
        2:1 & switch\_dbg\_sel & WR & switch dbg select. \newline 0: LINC2PAD. lin controller is selected to be debug by pad.\newline 1: LINSPHY2PAD. lin slave phy is selected to be debug by pad.\newline 2: LINMPHY2PAD. lin master phy is selected to be debug by pad.\\ \hline
        0:0 & switch\_dbg\_en & WR & switch dbg enable. \newline 0: DISABLE. debug disable.\newline 1: ENABLE. debug enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINPHYCFG}
Address: 0x4000A110. Reset: 0x00000000
\newline 
LIN PHYCFG Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & Reserve & RO & Reserve.\\ \hline
        23:16 & TXDUTCNT & WR & tx duty count\\ \hline
        15:4 & Reserve & RO & Reserve.\\ \hline
        3:3 & DUTSEL & WR & 0: duty increment; 1: duty decrement\\ \hline
        2:2 & DUTEN & WR & duty set enable\\ \hline
        1:1 & MTOTEN & WR & master timeout detect enable\\ \hline
        0:0 & STOTEN & WR & slave timeout detect enable\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINPHYIE}
Address: 0x4000A114. Reset: 0x00000000
\newline 
LIN PHYIE Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:2 & Reserve & RO & Reserve.\\ \hline
        1:1 & MTXTOE & WR & master tx timeout enable\\ \hline
        0:0 & STXTOE & WR & slave tx timeout enable\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINPHYSR}
Address: 0x4000A118. Reset: 0x00000000
\newline 
LIN PHY Stauts Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:2 & Reserve & RO & Reserve.\\ \hline
        1:1 & MTXTOF & RO & master tx timeout status\\ \hline
        0:0 & STXTOF & RO & slave tx timeout status\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINPHYCLR}
Address: 0x4000A11C. Reset: 0x00000000
\newline 
LIN PHY Stauts Clear Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:2 & Reserve & RO & Reserve.\\ \hline
        1:1 & MTXTOCLR & WO & slave tx timeout status clear\\ \hline
        0:0 & STXTOCLR & WO & slave tx timeout status clear\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINPHYMTOCNT}
Address: 0x4000A120. Reset: 0x000FA000
\newline 
LIN PHY Timeout Count Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:22 & Reserve & RO & Reserve.\\ \hline
        21:0 & MTOT & WR & master tx timeout count\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LINPHYSTOCNT}
Address: 0x4000A124. Reset: 0x000FA000
\newline 
LIN PHY Timeout Count Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:22 & Reserve & RO & Reserve.\\ \hline
        21:0 & STOT & WR & slave tx timeout count\\ \hline
		\end{xtabular}
	\end{center}

LIN address end \newline
WWDG address start \newline
\subsubsection{CR}
Address: 0x40009000. Reset: 0x0000007F
\newline 
Control register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:8 & Reserve & RO & Reserve.\\ \hline
        7:7 & WDGA & WR & Activation bit.\\ \hline
        6:0 & T & WR & 7-bit counter\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{CFR}
Address: 0x40009004. Reset: 0x0000007F
\newline 
Configuration register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:10 & Reserve & RO & Reserve.\\ \hline
        9:9 & EWI & WR & Early wakeup interrupt\\ \hline
        8:7 & WDGTB & WR & prescaler\newline 0: Div1\newline 1: Div2\newline 2: Div4\newline 3: Div8\\ \hline
        6:0 & W & WR & Window value\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SR}
Address: 0x40009008. Reset: 0x00000000
\newline 
Status register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & EWIF & WR & Early wakeup interrupt flag\\ \hline
		\end{xtabular}
	\end{center}

WWDG address end \newline
RCC address start \newline
\subsubsection{CLKDIVR}
Address: 0x40003000. Reset: 0x00000004
\newline 
System Clock Divider Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:4 & Reserve & RO & Reserve.\\ \hline
        3:0 & CLKDIV & WR & System clock dividor. SysClk = 32MHz / CLKDIV\newline 1: DIV2\newline 2: DIV4\newline 3: DIV6\newline 4: DIV8\newline 5: DIV10\newline 6: DIV12\newline 7: DIV14\newline 8: DIV16\newline 9: DIV18\newline 10: DIV20\newline 11: DIV22\newline 12: DIV24\newline 13: DIV26\newline 14: DIV28\newline 15: DIV30\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{PERICLKER}
Address: 0x40003004. Reset: 0x000001E2
\newline 
Peripheral Clock Enable Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:9 & Reserve & RO & Reserve.\\ \hline
        8:8 & GPIO & WR & GPIO module clock enable.\\ \hline
        7:7 & ADCCTRL & WR & ADCCTRL module clock enable.\\ \hline
        6:6 & LEDCTRL & WR & LEDCTRL module clock enable.\\ \hline
        5:5 & SYSCTRL & WR & SYSCTRL module clock enable.\\ \hline
        4:4 & TIM0 & WR & TIM0 module clock enable.\\ \hline
        3:3 & TIM1 & WR & TIM1 module clock enable.\\ \hline
        2:2 & TIM2 & WR & TIM2 module clock enable.\\ \hline
        1:1 & LIN & WR & LINCTRL module clock enable.\\ \hline
        0:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SYSRSTR}
Address: 0x40003100. Reset: 0x00000000
\newline 
System Reset Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & KEY & WR & The SYSRST bit protection KEY.\\ \hline
        23:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & SYSRST & WR & System reset. Only when KEY is 0x5A, writing this bit is effective.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{PERIRSTR}
Address: 0x40003104. Reset: 0x00000000
\newline 
Peripheral Reset Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:9 & Reserve & RO & Reserve.\\ \hline
        8:8 & GPIO & WR & GPIO module reset.\newline 0: RST\_RELEASE. Release GPIO module reset state.\newline 1: RST\_HOLD. Hold GPIO module reset state.\\ \hline
        7:7 & ADCCTRL & WR & ADCCTRL module reset.\newline 0: RST\_RELEASE. Release ADCCTRL module reset state.\newline 1: RST\_HOLD. Hold ADCCTRL module reset state.\\ \hline
        6:6 & LEDCTRL & WR & LEDCTRL module reset.\newline 0: RST\_RELEASE. Release LEDCTRL module reset state.\newline 1: RST\_HOLD. Hold LEDCTRL module reset state.\\ \hline
        5:5 & SYSCTRL & WR & SYSCTRL module reset.\newline 0: RST\_RELEASE. Release SYSCTRL module reset state.\newline 1: RST\_HOLD. Hold SYSCTRL module reset state.\\ \hline
        4:4 & TIM0 & WR & TIM0 module reset.\newline 0: RST\_RELEASE. Release TIM0 module reset state.\newline 1: RST\_HOLD. Hold TIM0 module reset state.\\ \hline
        3:3 & TIM1 & WR & TIM1 module reset.\newline 0: RST\_RELEASE. Release TIM1 module reset state.\newline 1: RST\_HOLD. Hold TIM1 module reset state.\\ \hline
        2:2 & TIM2 & WR & TIM2 module reset.\newline 0: RST\_RELEASE. Release TIM2 module reset state.\newline 1: RST\_HOLD. Hold TIM2 module reset state.\\ \hline
        1:1 & LIN & WR & LINCTRL module reset.\newline 0: RST\_RELEASE. Release LINCTRL module reset state.\newline 1: RST\_HOLD. Hold LINCTRL module reset state.\\ \hline
        0:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{RSTFR}
Address: 0x40003108. Reset: 0x00000001
\newline 
Reset Flag Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:4 & Reserve & RO & Reserve.\\ \hline
        3:0 & RSTF & RO & Indicate the last reset source.\newline 0x0: None. No reset event.\newline 0x1: POR. Power on reset.\newline 0x2: WWDG. WWDG timeout reset.\newline 0x3: SYSRST. Reset by setting SYSRSTR.SYSRST.\newline 0x4: CORERST. CPU core reset.\newline 0x5: VBATUV. Battery voltage under threshold reset.\newline 0x6: VBATOV. Battery voltage over threshold reset.\newline 0x7: OTW. Temperature measured by ADC over threshold reset.\newline 0x8: LDO50OV. LDO50 voltage over monitor threshold reset.\newline 0x9: LDO50UV. LDO50 voltage under monitor threshold reset.\newline 0xA: LDO15OV. LDO15 voltage over monitor threshold reset.\newline 0xB: LDO15UV. LDO15 voltage under monitor threshold reset.\newline 0xC: OTP. Temperature over monitor threshold reset.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LDO15MONR}
Address: 0x40003110. Reset: 0x00000880
\newline 
LDO15 Monitor Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:12 & Reserve & RO & Reserve.\\ \hline
        11:8 & OVTH & WR & Selects the reference level for LDO1P5 over threshold monitor. \newline range: 1.52V~1.82V.\newline default : 0x8, Vrise = 1.65V, hysteresis = 50mV.\\ \hline
        7:4 & UVTH & WR & Selects the reference level for LDO1P5 under threshold monitor. \newline range: 1.18V~1.65V.\newline default : 0x8, Vrise = 1.35V, hysteresis = 50mV.\\ \hline
        3:2 & Reserve & RO & Reserve.\\ \hline
        1:1 & OVEN & WR & LDO 1.5V voltage over threshold monitor enable.\\ \hline
        0:0 & UVEN & WR & LDO 1.5V voltage under threshold monitor enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{VBATMONR}
Address: 0x40003114. Reset: 0x00082130
\newline 
VBAT Monitor Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:20 & Reserve & RO & Reserve.\\ \hline
        19:16 & OVTH & WR & Battery voltage over threshold. The following table is based on OVHYS is set to 0.\newline 0x0: Vrise:14.29, Vfall:14.07,hysteresis:220mV;\newline 0x1: Vrise:14.74, Vfall:14.51,hysteresis:230mV;\newline 0x2: Vrise:14.98, Vfall:14.22,hysteresis:240mV;\newline 0x3: Vrise:15.73, Vfall:14.47,hysteresis:260mV;\newline 0x4: Vrise:16.30, Vfall:16.02,hysteresis:280mV;\newline 0x5: Vrise:16.90, Vfall:16.58,hysteresis:320mV;\newline 0x6: Vrise:17.54, Vfall:17.22,hysteresis:320mV;\newline 0x7: Vrise:18.24, Vfall:17.90,hysteresis:360mV;\newline 0x8: Vrise:19.04, Vfall:18.64,hysteresis:400mV; (Default)\newline 0x9: Vrise:19.44, Vfall:19.87,hysteresis:440mV;\newline 0xA: Vrise:20.80, Vfall:20.32,hysteresis:480mV;\newline 0xB: Vrise:21.82, Vfall:21.29,hysteresis:530mV;\newline 0xC: Vrise:22.97, Vfall:22.39,hysteresis:590mV;\newline 0xD: Vrise:24.24, Vfall:23.58,hysteresis:660mV;\newline 0xE: Vrise:25.67, Vfall:24.93,hysteresis:740mV;\newline 0xF: Vrise:27.28, Vfall:26.44,hysteresis:840mV.\\ \hline
        15:15 & Reserve & RO & Reserve.\\ \hline
        14:13 & OVHYS & WR & Battery voltage over threshold hysteresis. The following data is based on OVTH is set to 0x8.\newline 0: L0\_0P40. 0.40V\newline 1: L1\_1P02. 1.02V\newline 2: L2\_1P69. 1.69V\newline 3: L3\_2P37. 2.37V\\ \hline
        12:12 & OVEN & WR & Battery voltage over threshold monitor enable.\\ \hline
        11:10 & Reserve & RO & Reserve.\\ \hline
        9:8 & UVHYS & WR & Battery voltage under threshold hysteresis. The following data is based on UVTH is set to 0x3.\newline 0: L0\_0P08. 0.08V\newline 1: L1\_0P19. 0.19V\newline 2: L2\_0P28. 0.28V\newline 3: L3\_0P36. 0.36V\\ \hline
        7:4 & UVTH & WR & Battery voltage under threshold. The following table is based on UVHYS is set to 1.\newline 0x0: Vrise:5.00, Vfall:5.15,hysteresis:150mV;\newline 0x1: Vrise:5.14, Vfall:5.30,hysteresis:160mV;\newline 0x2: Vrise:5.31, Vfall:5.49,hysteresis:180mV;\newline 0x3: Vrise:5.48, Vfall:5.67,hysteresis:200mV; (Default)\newline 0x4: Vrise:5.68, Vfall:5.88,hysteresis:220mV;\newline 0x5: Vrise:5.88, Vfall:6.11,hysteresis:230mV;\newline 0x6: Vrise:6.11, Vfall:6.36,hysteresis:250mV;\newline 0x7: Vrise:6.36, Vfall:6.64,hysteresis:280mV;\newline 0x8: Vrise:6.61, Vfall:6.92,hysteresis:310mV; \newline 0x9: Vrise:6.91, Vfall:7.26,hysteresis:350mV;\newline 0xA: Vrise:7.26, Vfall:7.65,hysteresis:400mV;\newline 0xB: Vrise:7.64, Vfall:8.09,hysteresis:450mV;\newline 0xC: Vrise:8.10, Vfall:8.62,hysteresis:520mV;\newline 0xD: Vrise:8.60, Vfall:9.20,hysteresis:600mV;\newline 0xE: Vrise:9.20, Vfall:9.90,hysteresis:700mV;\newline 0xF: Vrise:9.88, Vfall:10.72,hysteresis:840mV.\\ \hline
        3:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & UVEN & WR & Battery voltage under threshold monitor enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LDO50MONR}
Address: 0x40003118. Reset: 0x00000880
\newline 
LDO 5V Monitor Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:12 & Reserve & RO & Reserve.\\ \hline
        11:8 & OVTH & WR & Selects the reference level for LDO1P5 over threshold monitor. \newline range: 5.2V~6.8V.\newline default : 0x8, Vrise = 6V, hysteresis = 190mV.\\ \hline
        7:4 & UVTH & WR & Selects the reference level for LDO1P5 under threshold monitor. \newline range: 3.6V~4.7V.\newline default : 0x8, Vrise = 4V, hysteresis = 220mV.\\ \hline
        3:2 & LDO50MEASEN & WR & LDO 5V measure enable. Only when this bit is set can ADC measures LDO 5V.\\ \hline
        1:1 & OVEN & WR & LDO 5V voltage over threshold monitor enable.\\ \hline
        0:0 & UVEN & WR & LDO 5V voltage under threshold monitor enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{OTPR}
Address: 0x4000311C. Reset: 0x00000080
\newline 
Over Temperature Protection Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:8 & Reserve & RO & Reserve.\\ \hline
        7:4 & OTPTH & WR & Select over-temperature threshold for OTP.\newline Default: Rising:155.4C, Falling: 136.4C, hysteresis: 20C\\ \hline
        3:2 & Reserve & RO & Reserve.\\ \hline
        1:1 & BGBFEN & WR & BandGap Buffer Enable. Before using temperature sensor, set this bit.\\ \hline
        0:0 & OTPEN & WR & Over Temperature Protection Enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SAFRSTER}
Address: 0x40003120. Reset: 0x00000000
\newline 
Safty Reset Enable Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:8 & Reserve & RO & Reserve.\\ \hline
        7:7 & OTP & WR & Setting this bit will lead to system reset if OTP event is deteced by over-temperature monitor.\\ \hline
        6:6 & LDO50UV & WR & Setting this bit will lead to system reset if LDO5V voltage is under monitor threshold.\\ \hline
        5:5 & LDO50OV & WR & Setting this bit will lead to system reset if LDO5V voltage is over monitor threshold.\\ \hline
        4:4 & OTW & WR & Setting this bit will lead to system reset if OTW event is deteced by ADC.\\ \hline
        3:3 & LDO15UV & WR & Setting this bit will lead to system reset if LDO1V5 voltage is under monitor threshold.\\ \hline
        2:2 & LDO15OV & WR & Setting this bit will lead to system reset if LDO1V5 voltage is over monitor threshold.\\ \hline
        1:1 & VBATUV & WR & Setting this bit will lead to system reset if battery voltage is under monitor threshold.\\ \hline
        0:0 & VBATOV & WR & Setting this bit will lead to system reset if battery voltage is over monitor threshold.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SAFIFR}
Address: 0x40003124. Reset: 0x00000000
\newline 
RCC Interrupt Flag Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:10 & Reserve & RO & Reserve.\\ \hline
        9:9 & VBATUVQ & RO & Battey voltage under monitor threshold quick interrupt flag.\\ \hline
        8:8 & VBATOVQ & RO & Battey voltage over monitor threshold quick interrupt flag.\\ \hline
        7:7 & OTP & RO & Over temperature protection interrupt flag.\\ \hline
        6:6 & LDO50UV & RO & LDO50 voltage under monitor threshold interrupt flag.\\ \hline
        5:5 & LDO50OV & RO & LDO50 voltage over monitor threshold interrupt flag.\\ \hline
        4:4 & Reserve & RO & Reserve.\\ \hline
        3:3 & LDO15UV & RO & LDO15 voltage under monitor threshold interrupt flag.\\ \hline
        2:2 & LDO15OV & RO & LDO15 voltage over threshold interrupt flag.\\ \hline
        1:1 & VBATUV & RO & Battery voltage under monitor threshold interrupt flag.\\ \hline
        0:0 & VBATOV & RO & Battery voltage over monitor threshold interrupt flag.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SAFIER}
Address: 0x40003128. Reset: 0x00000000
\newline 
RCC Interrupt Enable Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:10 & Reserve & RO & Reserve.\\ \hline
        9:9 & VBATUVQ & WR & Battery voltage under monitor threshold quick interrupt enable.\\ \hline
        8:8 & VBATOVQ & WR & Battery voltage over monitor threshold quick interrupt enable.\\ \hline
        7:7 & OTP & WR & Temperature monited over monitor threshold interrupt enable.\\ \hline
        6:6 & LDO50UV & WR & LDO50 voltage under monitor threshold interrupt enable.\\ \hline
        5:5 & LDO50OV & WR & LDO50 voltage over monitor threshold interrupt enable.\\ \hline
        4:4 & Reserve & RO & Reserve.\\ \hline
        3:3 & LDO15UV & WR & LDO15 voltage under monitor threshold interrupt enable.\\ \hline
        2:2 & LDO15OV & WR & LDO15 voltage over monitor threshold interrupt enable.\\ \hline
        1:1 & VBATUV & WR & Battery voltage under monitor threshold interrupt enable.\\ \hline
        0:0 & VBATOV & WR & Battery voltage over monitor threshold interrupt enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SAFICLR}
Address: 0x4000312C. Reset: 0x00000000
\newline 
RCC Interrupt Flag Clear Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:10 & Reserve & RO & Reserve.\\ \hline
        9:9 & VBATUVQ & WO & Write 1 to clear VBATUVQIF.\\ \hline
        8:8 & VBATOVQ & WO & Write 1 to clear VBATOVQIF.\\ \hline
        7:7 & OTP & WO & Write 1 to clear OPTIF.\\ \hline
        6:6 & LDO50UV & WO & Write 1 to clear LDO50UVIF.\\ \hline
        5:5 & LDO50OV & WO & Write 1 to clear LDO50OVIF.\\ \hline
        4:4 & Reserve & RO & Reserve.\\ \hline
        3:3 & LDO15UV & WO & Write 1 to clear LDO15UVIF.\\ \hline
        2:2 & LDO15OV & WO & Write 1 to clear LDO15OVIF.\\ \hline
        1:1 & VBATUV & WO & Write 1 to clear VBATUVIF.\\ \hline
        0:0 & VBATOV & WO & Write 1 to clear VBATOVIF.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{BIASER}
Address: 0x40003130. Reset: 0x00000000
\newline 
BIAS Enable Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & BIASEN & WR & Enable ibias.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SSCR}
Address: 0x40003200. Reset: 0x00100810
\newline 
Spread Spectrum Clocking Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:23 & Reserve & RO & Reserve.\\ \hline
        22:16 & freq\_stay & WR & \\ \hline
        15:12 & Reserve & RO & Reserve.\\ \hline
        11:8 & freq\_range & WR & \\ \hline
        7:4 & freq\_step & WR & \\ \hline
        3:3 & en & WR & \\ \hline
        2:2 & Reserve & RO & Reserve.\\ \hline
        1:0 & mode & WR & 0: SawtoothUp\newline 1: SawtoothUpDown\newline 2: SawtoothDown\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{CLKDBGR}
Address: 0x40003180. Reset: 0x00000000
\newline 
Clock Debug Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:2 & Reserve & RO & Reserve.\\ \hline
        1:1 & LINBAUDCLK\_RES & WR & \\ \hline
        0:0 & MCO & WR & Microcontroller clock output.\newline 0: RCOSC. High frequncy clock, which is diveded to 512KHz.\newline 1: LPOSC. Low frequncy 256KHz clock .\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{VBATUVCR0}
Address: 0x40003204. Reset: 0x00100001
\newline 
Battery Under Threshold Debounce Control Register0. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:20 & DBNCTHHQ & WR & Under voltage debounce quick threshold for 0to1 transition.\newline It will require the VBATUVQ event to stay low for (UVDBNCTH1Q + 1) system clock.\\ \hline
        19:18 & Reserve & RO & Reserve.\\ \hline
        17:0 & DBNCTHH & WR & Under voltage debounce threshold for 0to1 transition.\newline It will require the VBATUV event to stay low for (UVDBNCTH1 + 1) system clock.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{VBATUVCR1}
Address: 0x40003208. Reset: 0x003FFFF0
\newline 
Battery Under Threshold Debounce Control Register1. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:22 & Reserve & RO & Reserve.\\ \hline
        21:4 & DBNCTHL & WR & Under voltage debounce threshold for 1to0 transition.\newline It will require the VBATUV event to stay high for (UVDBNCTH1 + 1) system clock.\\ \hline
        3:2 & Reserve & RO & Reserve.\\ \hline
        1:1 & UVQEN & WR & Batter under voltage detection enable.\\ \hline
        0:0 & UVEN & WR & Batter under voltage quick detection enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{VBATOVCR0}
Address: 0x4000320C. Reset: 0x00100001
\newline 
Battery Over Threshold Debounce Control Register0. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:20 & DBNCTHHQ & WR & Under voltage debounce quick threshold for 0to1 transition.\newline It requires the VBATOVQ event to stay low for (OVDBNCTH1Q + 1) system clock.\\ \hline
        19:18 & Reserve & RO & Reserve.\\ \hline
        17:0 & DBNCTHH & WR & Under voltage debounce threshold for 0to1 transition.\newline It requires the VBATOV event to stay low for (OVDBNCTH1 + 1) system clock.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{VBATOVCR1}
Address: 0x40003210. Reset: 0x003FFFF0
\newline 
Battery Over Threshold Debounce Control Register1. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:22 & Reserve & RO & Reserve.\\ \hline
        21:4 & DBNCTHL & WR & Over voltage debounce threshold for 1to0 transition.\newline It requires the battery voltage falling below (VBATMONR.OVTH - VBATMONR.OVHYS) for at least(OVDBNCTHL + 1) system clock.\\ \hline
        3:2 & Reserve & RO & Reserve.\\ \hline
        1:1 & OVQEN & WR & Batter over voltage detection enable.\\ \hline
        0:0 & OVEN & WR & Batter over voltage quick detection enable.\\ \hline
		\end{xtabular}
	\end{center}

RCC address end \newline
TIM0 address start \newline
\subsubsection{CR}
Address: 0x40006000. Reset: 0x00000000
\newline 
Control whether to output trigger signal to TRGMUX when period overflows. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:3 & Reserve & RO & Reserve.\\ \hline
        2:2 & TGOUTEN & WR & Control whether to output trigger signal to TRGMUX when period overflows. \newline 0: DIS. When period overflows, do not output trigger signal to TRGMUX. \newline 1: EN. When period overflows, output trigger signal to TRGMUX.\\ \hline
        1:1 & TGSRC & WR & Select the TIM enable source. \newline 0: HARDSRC. TIM is enabled by signal from TRGMUX. \newline 1: SOFTSRC. TIM is enabled by EN.\\ \hline
        0:0 & EN & WR & TIM enables.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{CNTR}
Address: 0x40006004. Reset: 0x00000000
\newline 
Count Value Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:16 & Reserve & RO & Reserve.\\ \hline
        15:0 & CNT & RO & Count value.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IER}
Address: 0x40006008. Reset: 0x00000000
\newline 
Interrupt Enable Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & OVE & WR & Overflow interrupt enables the controller.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SR}
Address: 0x4000600C. Reset: 0x00000000
\newline 
State Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & OVF & WO & Overflow interrupt flag.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{ICLR}
Address: 0x40006010. Reset: 0x00000000
\newline 
Clear Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & OVCLR & WO & Overflow interrupt clear\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{PRDR}
Address: 0x40006014. Reset: 0x0000FFFF
\newline 
Period Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:16 & Reserve & RO & Reserve.\\ \hline
        15:0 & PRD & WR & Period register. Overflow when the count is equal to PRD.\\ \hline
		\end{xtabular}
	\end{center}

TIM0 address end \newline
TIM1 address start \newline
\subsubsection{CR}
Address: 0x40007000. Reset: 0x00000000
\newline 
Control whether to output trigger signal to TRGMUX when period overflows. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:3 & Reserve & RO & Reserve.\\ \hline
        2:2 & TGOUTEN & WR & Control whether to output trigger signal to TRGMUX when period overflows. \newline 0: DIS. When period overflows, do not output trigger signal to TRGMUX. \newline 1: EN. When period overflows, output trigger signal to TRGMUX.\\ \hline
        1:1 & TGSRC & WR & Select the TIM enable source. \newline 0: HARDSRC. TIM is enabled by signal from TRGMUX. \newline 1: SOFTSRC. TIM is enabled by EN.\\ \hline
        0:0 & EN & WR & TIM enables.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{CNTR}
Address: 0x40007004. Reset: 0x00000000
\newline 
Count Value Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:16 & Reserve & RO & Reserve.\\ \hline
        15:0 & CNT & RO & Count value.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IER}
Address: 0x40007008. Reset: 0x00000000
\newline 
Interrupt Enable Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & OVE & WR & Overflow interrupt enables the controller.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SR}
Address: 0x4000700C. Reset: 0x00000000
\newline 
State Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & OVF & WO & Overflow interrupt flag.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{ICLR}
Address: 0x40007010. Reset: 0x00000000
\newline 
Clear Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & OVCLR & WO & Overflow interrupt clear\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{PRDR}
Address: 0x40007014. Reset: 0x0000FFFF
\newline 
Period Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:16 & Reserve & RO & Reserve.\\ \hline
        15:0 & PRD & WR & Period register. Overflow when the count is equal to PRD.\\ \hline
		\end{xtabular}
	\end{center}

TIM1 address end \newline
TIM2 address start \newline
\subsubsection{CR}
Address: 0x40008000. Reset: 0x00000000
\newline 
Control the output of TRIG when overflows occur. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:3 & Reserve & RO & Reserve.\\ \hline
        2:2 & TRGEN & WR & Control the output of TRIG when overflows occur.\\ \hline
        1:1 & EXTEN & WR & Control hardware trig counter counts.\\ \hline
        0:0 & EN & WR & Counter enables.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{CNTR}
Address: 0x40008004. Reset: 0x00000000
\newline 
Count Value Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:0 & CNT & RO & Count value.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IER}
Address: 0x40008008. Reset: 0x00000000
\newline 
Interrupt Enable Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & OVE & WR & Overflow interrupt enables the controller.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SR}
Address: 0x4000800C. Reset: 0x00000000
\newline 
State Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & OVF & WO & Overflow interrupt flag.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{ICLR}
Address: 0x40008010. Reset: 0x00000000
\newline 
Clear Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & OVCLR & WO & Overflow interrupt clear\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{PRDR}
Address: 0x40008014. Reset: 0xFFFFFFFF
\newline 
Period Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:0 & PRD & WR & Period register. Overflow when the count is equal to PRD.\\ \hline
		\end{xtabular}
	\end{center}

TIM2 address end \newline
ADCCTRL address start \newline
\subsubsection{CR0}
Address: 0x4000F000. Reset: 0x00000000
\newline 
ADC Control Register0. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:12 & TGSRC & WR & ADC trigger source seletection.\newline 0: SWSRC. Every time TGSW is set, a ADC trigger generates.\newline 1: HWSRC. ADCCtrl selects the trigger from TRGMUX.\\ \hline
        11:9 & Reserve & RO & Reserve.\\ \hline
        8:8 & TGSW & WR & This bit can only write 1 and will be cleared automatically.\newline Every time TGSW is set, a ADC software trigger generates.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:4 & SEQLEN & WR & ADC scanning sequnce length.\newline 0: LEN1. ADC scanning sequnce includes the channel defined in CHCFG[0].CHSEL.\newline 1: LEN2. ADC scanning sequnce includes the channels defined in CHCFG[0].CHSEL, CHCFG[1].CHSEL.\newline 2: LEN3. ADC scanning sequnce includes the channels defined in CHCFG[0].CHSEL, CHCFG[1].CHSEL,\newline CHCFG[2].CHSEL.\newline 2: LEN4. ADC scanning sequnce includes the channels defined in CHCFG[0].CHSEL, CHCFG[1].CHSEL,\newline CHCFG[2].CHSEL, CHCFG[3].CHSEL.\\ \hline
        3:3 & Reserve & RO & Reserve.\\ \hline
        2:2 & CYCLE & WR & ADCCtrl cycle scan mode.\newline \newline 0: DIS. ADC single scan mode. After finishing measuring a channel sequence, ADCCtrl stops until receiving a triger.\newline 1: EN. ADC cycle scan mode. \newline After finishing measuring a channel sequence, ADCCtrl continues measuring channels defined in CHCFG[x].CHSEL.\\ \hline
        1:1 & LPEN & WR & Low power mode enable. When in low power mode, a trigger can wakeup ADCCtrl.\\ \hline
        0:0 & ADEN & WR & ADC enable. Only when this bit is set, can RDY be set.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{CR1\_RES}
Address: 0x4000F004. Reset: 0x00005030
\newline 
ADC Control Register1. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:20 & Reserve & RO & Reserve.\\ \hline
        19:8 & TACTIVE & WR & Time for ADC from diable to active.\\ \hline
        7:0 & TLPACTIVE & WR & Time for ADC form exit-from-lowpower to active\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{OTWR}
Address: 0x4000F008. Reset: 0x00000000
\newline 
ADC Over Temperature Warning Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:28 & Reserve & RO & Reserve.\\ \hline
        27:16 & OTWTH & WR & When the measured temperature sensor code is above this value, OTW will be set.\\ \hline
        15:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & OTWEN & WR & Over temperature warning enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SR}
Address: 0x4000F00C. Reset: 0x00000000
\newline 
ADC Status Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:4 & Reserve & RO & Reserve.\\ \hline
        3:3 & RDY & RO & ADC is ready to work.\\ \hline
        2:2 & OTWF & RO & Chip temperature above threshold warning flag.\newline When temperature sensor code is above OTWTH and OTWEN is 1, this bit will be set.\\ \hline
        1:1 & TGERR & RO & Trigger error flag. This bit will set when ADCCtrl receives a new comming trigger before last scanning sequence finishes.\\ \hline
        0:0 & EOC & RO & The end flag of ADC converting. When ADCCtrl finishes measuring the channels defined in SEQLEN and CHCFG[x],\newline This bit will be set.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IER}
Address: 0x4000F010. Reset: 0x00000000
\newline 
ADC Interrupt Enable Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:3 & Reserve & RO & Reserve.\\ \hline
        2:2 & OTWIE & WR & Over temperature warning enable.\\ \hline
        1:1 & TGERRIE & WR & Trigger error interrupt enable.\\ \hline
        0:0 & EOCIE & WR & EOC interrupt Enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{ICLR}
Address: 0x4000F014. Reset: 0x00000000
\newline 
ADC Interrupt Clear Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:3 & Reserve & RO & Reserve.\\ \hline
        2:2 & OTWCLR & WO & Write 1 to clear OTWF.\\ \hline
        1:1 & TGERRCLR & WO & Write 1 to clear TGERR.\\ \hline
        0:0 & EOCCLR & WO & Write 1 to clear EOC.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{CHCFGR[0]}
Address: 0x4000F018. Reset: 0x06000000
\newline 
ADC Channel Configure Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & TSAMP & WR & The ADC sample time of annalog channel. Sample time  = (TSAMP + 1) * sysclk\\ \hline
        23:20 & Reserve & RO & Reserve.\\ \hline
        19:8 & CHDLY & WR & The channel guard delay time of ADC switching to measure next channel. Configure this register to satisfy annalog channel Tset.\newline Channel delay time  = (CHDLY + 1) * sysclk\\ \hline
        7:3 & Reserve & RO & Reserve.\\ \hline
        2:0 & CHSEL & WR & Select the ADC measuring analog channel.\newline \newline 0: VFW. The forward voltage of LED. \newline 1: VTEMP. The voltage of internal temperature sensor.\newline 2: DRV\_VREF. The reference voltage of current driver module.\newline 3: BG\_VREF. The reference voltage of bandgap.\newline 4: DVDD15. The voltage of digtal LDO.\newline 5: AVDD50. The voltage of analog LDO.\newline 6: VBAT. The voltage of extern battery supply.\newline 7: GPIO. The voltage of extern GPIO.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{CHCFGR[1]}
Address: 0x4000F01C. Reset: 0x06000000
\newline 
ADC Channel Configure Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & TSAMP & WR & The ADC sample time of annalog channel. Sample time  = (TSAMP + 1) * sysclk\\ \hline
        23:20 & Reserve & RO & Reserve.\\ \hline
        19:8 & CHDLY & WR & The channel guard delay time of ADC switching to measure next channel. Configure this register to satisfy annalog channel Tset.\newline Channel delay time  = (CHDLY + 1) * sysclk\\ \hline
        7:3 & Reserve & RO & Reserve.\\ \hline
        2:0 & CHSEL & WR & Select the ADC measuring analog channel.\newline \newline 0: VFW. The forward voltage of LED. \newline 1: VTEMP. The voltage of internal temperature sensor.\newline 2: DRV\_VREF. The reference voltage of current driver module.\newline 3: BG\_VREF. The reference voltage of bandgap.\newline 4: DVDD15. The voltage of digtal LDO.\newline 5: AVDD50. The voltage of analog LDO.\newline 6: VBAT. The voltage of extern battery supply.\newline 7: GPIO. The voltage of extern GPIO.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{CHCFGR[2]}
Address: 0x4000F020. Reset: 0x06000000
\newline 
ADC Channel Configure Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & TSAMP & WR & The ADC sample time of annalog channel. Sample time  = (TSAMP + 1) * sysclk\\ \hline
        23:20 & Reserve & RO & Reserve.\\ \hline
        19:8 & CHDLY & WR & The channel guard delay time of ADC switching to measure next channel. Configure this register to satisfy annalog channel Tset.\newline Channel delay time  = (CHDLY + 1) * sysclk\\ \hline
        7:3 & Reserve & RO & Reserve.\\ \hline
        2:0 & CHSEL & WR & Select the ADC measuring analog channel.\newline \newline 0: VFW. The forward voltage of LED. \newline 1: VTEMP. The voltage of internal temperature sensor.\newline 2: DRV\_VREF. The reference voltage of current driver module.\newline 3: BG\_VREF. The reference voltage of bandgap.\newline 4: DVDD15. The voltage of digtal LDO.\newline 5: AVDD50. The voltage of analog LDO.\newline 6: VBAT. The voltage of extern battery supply.\newline 7: GPIO. The voltage of extern GPIO.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{CHCFGR[3]}
Address: 0x4000F024. Reset: 0x06000000
\newline 
ADC Channel Configure Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & TSAMP & WR & The ADC sample time of annalog channel. Sample time  = (TSAMP + 1) * sysclk\\ \hline
        23:20 & Reserve & RO & Reserve.\\ \hline
        19:8 & CHDLY & WR & The channel guard delay time of ADC switching to measure next channel. Configure this register to satisfy annalog channel Tset.\newline Channel delay time  = (CHDLY + 1) * sysclk\\ \hline
        7:3 & Reserve & RO & Reserve.\\ \hline
        2:0 & CHSEL & WR & Select the ADC measuring analog channel.\newline \newline 0: VFW. The forward voltage of LED. \newline 1: VTEMP. The voltage of internal temperature sensor.\newline 2: DRV\_VREF. The reference voltage of current driver module.\newline 3: BG\_VREF. The reference voltage of bandgap.\newline 4: DVDD15. The voltage of digtal LDO.\newline 5: AVDD50. The voltage of analog LDO.\newline 6: VBAT. The voltage of extern battery supply.\newline 7: GPIO. The voltage of extern GPIO.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DATAR[0]}
Address: 0x4000F028. Reset: 0x00000000
\newline 
The result data of ADC measuring analog channel defined in CHSEL. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:12 & Reserve & RO & Reserve.\\ \hline
        11:0 & DATA & RO & Right alignment, no sign.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DATAR[1]}
Address: 0x4000F02C. Reset: 0x00000000
\newline 
The result data of ADC measuring analog channel defined in CHSEL. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:12 & Reserve & RO & Reserve.\\ \hline
        11:0 & DATA & RO & Right alignment, no sign.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DATAR[2]}
Address: 0x4000F030. Reset: 0x00000000
\newline 
The result data of ADC measuring analog channel defined in CHSEL. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:12 & Reserve & RO & Reserve.\\ \hline
        11:0 & DATA & RO & Right alignment, no sign.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DATAR[3]}
Address: 0x4000F034. Reset: 0x00000000
\newline 
The result data of ADC measuring analog channel defined in CHSEL. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:12 & Reserve & RO & Reserve.\\ \hline
        11:0 & DATA & RO & Right alignment, no sign.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{TEST\_RES}
Address: 0x4000F040. Reset: 0x00000000
\newline 
For Debug Usage 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:25 & Reserve & RO & Reserve.\\ \hline
        24:24 & RAWDATA\_EN & RO & \\ \hline
        23:22 & Reserve & RO & Reserve.\\ \hline
        21:21 & DEBUG\_DATA & RO & \\ \hline
        20:20 & DEBUG\_OUT & RO & \\ \hline
        19:19 & Reserve & RO & Reserve.\\ \hline
        18:16 & DEBUG\_IN & RO & \\ \hline
        15:10 & Reserve & RO & Reserve.\\ \hline
        9:8 & SEQ\_CTRL\_FSM & RO & \\ \hline
        7:3 & Reserve & RO & Reserve.\\ \hline
        2:0 & ANA\_CTRL\_FSM & RO & \\ \hline
		\end{xtabular}
	\end{center}

ADCCTRL address end \newline
LEDCTRL address start \newline
\subsubsection{DIVR}
Address: 0x4000E000. Reset: 0x00000000
\newline 
LED PWM counter division. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:4 & Reserve & RO & Reserve.\\ \hline
        3:0 & CLKDIV & WR & LED PWM counter division value.\newline 0x0: DIV1. Div by 1\newline 0x1: DIV2. Div by 2\newline 0x2: DIV4. Div by 4\newline 0x3: DIV8. Div by 8\newline 0x4: DIV16. Div by 16\newline 0x5: DIV32. Div by 32\newline 0x6: DIV64. Div by 64\newline 0x7: DIV128. Div by 128\newline 0x8: DIV256. Div by 256\newline 0x9: DIV512. Div by 512\newline 0xA: DIV1024. Div by 1024\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{PRDR}
Address: 0x4000E004. Reset: 0x0000FFFF
\newline 
Period of PWM 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:16 & Reserve & RO & Reserve.\\ \hline
        15:0 & PRD & WR & When upper counter reaches this value, a overflow event occors, and counter will return to 0. \newline PWM period = sys\_freq / (DIV * PRD).\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{CR}
Address: 0x4000E008. Reset: 0x00000000
\newline 
Control Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:9 & Reserve & RO & Reserve.\\ \hline
        8:8 & FRCEN & WR & Force mode enable.\newline 0: DIS. LED driver current is controlled by PMM.\newline 1: EN. LED driver current is controlled by the value in FRCCFG.\\ \hline
        7:7 & UPDATE & WR & When set, DIV, PRD, POL, PRISE,PFALL will update at next counter overflow time.\newline And this bit is cleared after finishing those parameter.\\ \hline
        6:4 & CHEN & WR & Channels enable is controlled by this 3bits.\newline bit0: CH0OUT Enable;\newline bit1: CH1OUT Enable;\newline bit2: CH2OUT Enable.\\ \hline
        3:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & CNTEN & WR & Counter enable is controlled by this bit.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{TGCFGR0}
Address: 0x4000E00C. Reset: 0x00000000
\newline 
Config Register 0 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:9 & Reserve & RO & Reserve.\\ \hline
        8:8 & POL2 & WR & Polarity of CH2\newline 0x0: NO\_INV. LED2 is controlled by CH2OUT.\newline 0x1: INV. LED2 is controlled by inverted CH2OUT.\\ \hline
        7:7 & POL1 & WR & Polarity of CH1\newline 0x0: NO\_INV. LED1 is controlled by CH1OUT.\newline 0x1: INV. LED1 is controlled by inverted CH1OUT.\\ \hline
        6:6 & POL0 & WR & Polarity of CH0\newline 0x0: NO\_INV. LED0 is controlled by CH0OUT.\newline 0x1: INV. LED0 is controlled by inverted CH0OUT.\\ \hline
        5:4 & TGEDSEL2 & WR & CH2OUT trigger output signal selection.\newline 0x0: NONE. No trigger signal output.\newline 0x1: POSED. Output trigger signal at postive edge of CH2OUT.\newline 0x2: NEGED. Output trigger signal at negtive edge of CH2OUT.\newline 0x3: OVED. Output trigger signal at period overflow of CH2OUT.\\ \hline
        3:2 & TGEDSEL1 & WR & CH1OUT trigger output signal selection.\newline 0x0: NONE. No trigger signal output.\newline 0x1: POSED. Output trigger signal at postive edge of CH1OUT.\newline 0x2: NEGED. Output trigger signal at negtive edge of CH1OUT.\newline 0x3: OVED. Output trigger signal at period overflow of CH1OUT.\\ \hline
        1:0 & TGEDSEL0 & WR & CH0OUT trigger output signal selection.\newline 0x0: NONE. No trigger signal output.\newline 0x1: POSED. Output trigger signal at postive edge of CH0OUT.\newline 0x2: NEGED. Output trigger signal at negtive edge of CH0OUT.\newline 0x3: OVED. Output trigger signal at period overflow of CH0OUT.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{TGCFGR1}
Address: 0x4000E010. Reset: 0x000000C0
\newline 
It depends on this bit whether to send trigger signal when counter overflows. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:9 & Reserve & RO & Reserve.\\ \hline
        8:8 & TGOVOUTEN & WR & It depends on this bit whether to send trigger signal when counter overflows.\\ \hline
        7:6 & VFWCH & WR & When LEDCTRL generates a trigger signal, VFWCH decides which LED small current drives.\newline 0: CH0. Small current drives LED0.\newline 1: CH1. Small current drives LED1.\newline 2: CH2. Small current drives LED2.\\ \hline
        5:5 & TGMODE2 & WR & CH2OUT edge trigger mode.\newline 0: SINGLE. CH2OUT edge event generates single trigger.\newline 1: CYCLE. CH2OUT edge event continues generating trigger until TGEDEN2 is 0.\\ \hline
        4:4 & TGMODE1 & WR & CH1OUT edge trigger mode.\newline 0: SINGLE. CH1OUT edge event generates single trigger.\newline 1: CYCLE. CH1OUT edge event continues generating trigger until TGEDEN1 is 0.\\ \hline
        3:3 & TGMODE0 & WR & CH0OUT edge trigger mode.\newline 0: SINGLE. CH0OUT edge event generates single trigger.\newline 1: CYCLE. CH0OUT edge event continues generating trigger until TGEDEN0 is 0.\\ \hline
        2:2 & TGOUTEN2 & WR & Enable CH2OUT edge hardware trigger if set. \newline When TGMODE2 in single mode, this bit will reset after first CH2OUT edge trigger.\\ \hline
        1:1 & TGOUTEN1 & WR & Enable CH1OUT edge hardware trigger if set. \newline When TGMODE1 in single mode, this bit will reset after first CH1OUT edge trigger.\\ \hline
        0:0 & TGOUTEN0 & WR & Enable CH0OUT edge hardware trigger if set. \newline When TGMODE0 in single mode, this bit will reset after first CH0OUT edge trigger.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{CNTR}
Address: 0x4000E014. Reset: 0x00000001
\newline 
Counter value of PWM. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:16 & Reserve & RO & Reserve.\\ \hline
        15:0 & CNT & RO & Counter value of PWM.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{FRCCFGR}
Address: 0x4000E018. Reset: 0x00000000
\newline 
Force LED Configure Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:3 & Reserve & RO & Reserve.\\ \hline
        2:2 & CURSET2 & WR & LED2 current will turn on/off according to this configure when FRCEN is set.\newline 0: OFF. LED2 current turns off.\newline 1: ON. LED2 current turns on.\\ \hline
        1:1 & CURSET1 & WR & LED1 current will turn on/off according to this configure when FRCEN is set.\newline 0: OFF. LED1 current turns off.\newline 1: ON. LED1 current turns on.\\ \hline
        0:0 & CURSET0 & WR & LED0 current will turn on/off according to this configure when FRCEN is set.\newline 0: OFF. LED0 current turns off.\newline 1: ON. LED0 current turns on.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IER}
Address: 0x4000E01C. Reset: 0x00000000
\newline 
Interrupt Enable Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:8 & Reserve & RO & Reserve.\\ \hline
        7:7 & F2IE & WR & This bit decides whether to report interrput when counter equals to CH2 PFALL.\\ \hline
        6:6 & F1IE & WR & This bit decides whether to report interrput when counter equals to CH1 PFALL.\\ \hline
        5:5 & F0IE & WR & This bit decides whether to report interrput when counter equals to CH0 PFALL.\\ \hline
        4:4 & R2IE & WR & This bit decides whether to report interrput when counter equals to CH2 PRISE.\\ \hline
        3:3 & R1IE & WR & This bit decides whether to report interrput when counter equals to CH1 PRISE.\\ \hline
        2:2 & R0IE & WR & This bit decides whether to report interrput when counter equals to CH0 PRISE.\\ \hline
        1:1 & UPIE & WR & This bit decides whether to report interrput when PWM parameter is updated.\\ \hline
        0:0 & OVIE & WR & This bit decides whether to report interrput when counter reaches PRD.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFR}
Address: 0x4000E020. Reset: 0x00000000
\newline 
Interrupt Flag Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:8 & Reserve & RO & Reserve.\\ \hline
        7:7 & F2IF & RO & This bit indicates that F2I(Counter reaches CH2 PFALL value) occors. It can be cleared by F2ICLR.\\ \hline
        6:6 & F1IF & RO & This bit indicates that F1I(Counter reaches CH1 PFALL value) occors. It can be cleared by F1ICLR.\\ \hline
        5:5 & F0IF & RO & This bit indicates that F0I(Counter reaches CH0 PFALL value) occors. It can be cleared by F0ICLR.\\ \hline
        4:4 & R2IF & RO & This bit indicates that R2I(Counter reaches CH2 PRISE value) occors. It can be cleared by R2ICLR.\\ \hline
        3:3 & R1IF & RO & This bit indicates that R1I(Counter reaches CH1 PRISE value) occors. It can be cleared by R1ICLR.\\ \hline
        2:2 & R0IF & RO & This bit indicates that R0I(Counter reaches CH0 PRISE value) occors. It can be cleared by R0ICLR.\\ \hline
        1:1 & UPIF & RO & This bit indicates that UPI(PWM parameters updates) occors. It can be cleared by UPICLR.\\ \hline
        0:0 & OVIF & RO & This bit indicates that OVI(Counter reaches PRD) occors. It can be cleared by OVICLR.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{ICLR}
Address: 0x4000E024. Reset: 0x00000000
\newline 
Interrupt Clear Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:8 & Reserve & RO & Reserve.\\ \hline
        7:7 & F2ICLR & WO & This bit is used to clear F2IF.\\ \hline
        6:6 & F1ICLR & WO & This bit is used to clear F1IF.\\ \hline
        5:5 & F0ICLR & WO & This bit is used to clear F0IF.\\ \hline
        4:4 & R2ICLR & WO & This bit is used to clear R2IF.\\ \hline
        3:3 & R1ICLR & WO & This bit is used to clear R1IF.\\ \hline
        2:2 & R0ICLR & WO & This bit is used to clear R0IF.\\ \hline
        1:1 & UPICLR & WO & This bit is used to clear UPIF.\\ \hline
        0:0 & OVICLR & WO & This bit is used to clear OVIF.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DUTYCFGR[0]}
Address: 0x4000E028. Reset: 0x00000000
\newline 
PWM Channel Configure Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:16 & PFALL & WR & CHxOUT sets low when counter equals to PFALL\\ \hline
        15:0 & PRISE & WR & CHxOUT sets high when counter equals to PRISE\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DUTYCFGR[1]}
Address: 0x4000E02C. Reset: 0x00000000
\newline 
PWM Channel Configure Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:16 & PFALL & WR & CHxOUT sets low when counter equals to PFALL\\ \hline
        15:0 & PRISE & WR & CHxOUT sets high when counter equals to PRISE\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DUTYCFGR[2]}
Address: 0x4000E030. Reset: 0x00000000
\newline 
PWM Channel Configure Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:16 & PFALL & WR & CHxOUT sets low when counter equals to PFALL\\ \hline
        15:0 & PRISE & WR & CHxOUT sets high when counter equals to PRISE\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{OVTOGCR}
Address: 0x4000E034. Reset: 0x00000000
\newline 
Toggle GPIO when PWM counter overflows 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & OVTOGEN & WR & If enabled, GPIO3-5 will toggle when PWM counter overflows if GPIO3-5 is alternating as PWM\_CHx mode.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LEDCURCFGR[0]}
Address: 0x4000E050. Reset: 0x000001F4
\newline 
LED Current Config Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:9 & Reserve & RO & Reserve.\\ \hline
        8:0 & CUR & WR & Setting the LED drive current value. Its step is 120uA.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LEDCURCFGR[1]}
Address: 0x4000E054. Reset: 0x000001F4
\newline 
LED Current Config Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:9 & Reserve & RO & Reserve.\\ \hline
        8:0 & CUR & WR & Setting the LED drive current value. Its step is 120uA.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LEDCURCFGR[2]}
Address: 0x4000E058. Reset: 0x000001F4
\newline 
LED Current Config Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:9 & Reserve & RO & Reserve.\\ \hline
        8:0 & CUR & WR & Setting the LED drive current value. Its step is 120uA.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{VFWCURCFGR}
Address: 0x4000E05C. Reset: 0x000000C8
\newline 
Setting the small drive current value. Its step is 10uA. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:8 & Reserve & RO & Reserve.\\ \hline
        7:0 & CUR & WR & Setting the small drive current value. Its step is 10uA.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LEDCFGR}
Address: 0x4000E060. Reset: 0x00000010
\newline 
LDMOS bias select 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:13 & Reserve & RO & Reserve.\\ \hline
        12:11 & BIASSEL\_RES & WR & LDMOS bias select\\ \hline
        10:10 & SHORT\_RES & WR & LED short\\ \hline
        9:9 & OPEN\_RES & WR & LED open\\ \hline
        8:7 & SRR & WR & Rising slew rate control.\newline 0: NS20. 20ns.\newline 1: NS30. 30ns.\newline 2: NS40. 40ns.\newline 3: NS50. 50ns.\\ \hline
        6:6 & SRF & WR & Falling slew rate control.\newline 0: NS5. 5ns.\newline 1: NS20. 20ns.\\ \hline
        5:5 & BIASEN & WR & Enabling the bias current for the LED\\ \hline
        4:4 & VFWHW & WR & VFW control mode selection.\newline 0: SOFT. Software control mode. In this mode, small current turns on/off by setting VFWEN.\newline 1: HARD. Hardware control mode. In this mode, small current turns on every time LEDCTRL generates a trigger.\\ \hline
        3:3 & VFWEN & WR & Enable the small current. Make sure this bit is set before ADC measures VFW.\\ \hline
        2:0 & PUEN & WR & Enable LEDx IO pull-up resistance.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LEDSWSELR}
Address: 0x4000E064. Reset: 0x00000000
\newline 
LED0 current switch control selection 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:3 & Reserve & RO & Reserve.\\ \hline
        2:2 & SW2 & WR & LED2 current switch control selection \newline 2: PWM. LED2 current switch controlled by PWM.\newline 1: DIRECT. LED2 current switch controlled by LEDSWOUT.\\ \hline
        1:1 & SW1 & WR & LED1 current switch control selection \newline 1: PWM. LED1 current switch controlled by PWM.\newline 1: DIRECT. LED1 current switch controlled by LEDSWOUT.\\ \hline
        0:0 & SW0 & WR & LED0 current switch control selection \newline 0: PWM. LED0 current switch controlled by PWM.\newline 1: DIRECT. LED0 current switch controlled by LEDSWOUT.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LEDSWOUTR}
Address: 0x4000E068. Reset: 0x00000000
\newline 
LED0 current direct control. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:3 & Reserve & RO & Reserve.\\ \hline
        2:2 & OUT2 & WR & LED2 current direct control.\newline 0: CLOSE. Close LED2 current.\newline 1: OPEN. Open LED2 current.\\ \hline
        1:1 & OUT1 & WR & LED1 current direct control.\newline 0: CLOSE. Close LED1 current.\newline 1: OPEN. Open LED1 current.\\ \hline
        0:0 & OUT0 & WR & LED0 current direct control.\newline 0: CLOSE. Close LED0 current.\newline 1: OPEN. Open LED0 current.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{PGACFGR}
Address: 0x4000E06C. Reset: 0x00000030
\newline 
PGA enable. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:8 & Reserve & RO & Reserve.\\ \hline
        7:7 & BASESEL & WR & PGA VBAT GPIO gain.\\ \hline
        6:6 & GAIN & WR & PGA gain. 0:1/4; 1:1/2\\ \hline
        5:4 & PGACH & WR & PGA selection\\ \hline
        3:2 & SPEED\_RES & WR & PGA SPEED\\ \hline
        1:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & PGAEN & WR & PGA enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LEDDBG\_RES}
Address: 0x4000E070. Reset: 0x00000000
\newline 
dbg sel. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:3 & Reserve & RO & Reserve.\\ \hline
        2:0 & DBG & WR & dbg sel.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LEDDBGOUT\_RES}
Address: 0x4000E074. Reset: 0x00000000
\newline 
dbg out. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & DBGOUT & RO & dbg out.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{PGADBG\_RES}
Address: 0x4000E078. Reset: 0x00000000
\newline 
pga dbg. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:3 & Reserve & RO & Reserve.\\ \hline
        2:0 & DBG & WR & pga dbg.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{PGADBGOUT\_RES}
Address: 0x4000E07C. Reset: 0x00000000
\newline 
pga dbg out. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & PGADBGOUT & RO & pga dbg out.\\ \hline
		\end{xtabular}
	\end{center}

LEDCTRL address end \newline
FMC address start \newline
\subsubsection{CR}
Address: 0x40004000. Reset: 0x00000002
\newline 
Flash Control Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:28 & Reserve & RO & Reserve.\\ \hline
        27:27 & FILTER & WR & When target byte and data stored in target address are 0xff, this bit select whether to program 0xff again.\newline 0x0: DIS. Program flash even though target byte data and data stored at target address are 0x0FF.\newline Be careful that this function should be disabed when system clock is not 16MHz.\newline 0x1: EN. Bypass program flash when target byte data and data stored at target address are 0x0FF.\\ \hline
        26:26 & NVR & WR & When erase or program or regiser read NVR, need configure this bit.\newline 0x0: MAINFLASH. Erase or program Main Flash area.\newline 0x1: NVR. Erase or program NVR area.\\ \hline
        25:25 & READM1\_RES & WR & Margin read for program enable\\ \hline
        24:24 & READM0\_RES & WR & Margin read for erase enable\\ \hline
        23:23 & Reserve & RO & Reserve.\\ \hline
        22:22 & FLSDPEN & WR & Flash Depsleep Enable. If enabled, flash will jump into deepsleep mode when CPU enters lowpower mode \newline at the condition of setting SCR.SLEEPDEEP. Peripheral interrupt such as TIM, LIN, ADC can awake CPU lowpower mode\newline and thus awake flash deepsleep mode.\\ \hline
        21:21 & WPTNVR4\_RES & WR & Protect NVR 4\\ \hline
        20:20 & WPTNVR3\_RES & WR & Protect NVR 3\\ \hline
        19:19 & WPTNVR2 & WR & Protect NVR 2 from erasing and programing.\\ \hline
        18:18 & WPTNVR1 & WR & Protect NVR 1 from erasing and programing.\\ \hline
        17:17 & WPT60K & WR & Protect Main Flash [60K to 60+4K) from erasing and programing.\\ \hline
        16:16 & WPT56K & WR & Protect Main Flash [56K to 56+4K) from erasing and programing.\\ \hline
        15:15 & WPT52K & WR & Protect Main Flash [52K to 52+4K) from erasing and programing.\\ \hline
        14:14 & WPT48K & WR & Protect Main Flash [48K to 48+4K) from erasing and programing.\\ \hline
        13:13 & WPT44K & WR & Protect Main Flash [44K to 44+4K) from erasing and programing.\\ \hline
        12:12 & WPT40K & WR & Protect Main Flash [40K to 40+4K) from erasing and programing.\\ \hline
        11:11 & WPT36K & WR & Protect Main Flash [36K to 36+4K) from erasing and programing.\\ \hline
        10:10 & WPT32K & WR & Protect Main Flash [32K to 32+4K) from erasing and programing.\\ \hline
        9:9 & WPT28K & WR & Protect Main Flash [28K to 28+4K) from erasing and programing.\\ \hline
        8:8 & WPT24K & WR & Protect Main Flash [24K to 24+4K) from erasing and programing.\\ \hline
        7:7 & WPT20K & WR & Protect Main Flash [20K to 20+4K) from erasing and programing.\\ \hline
        6:6 & WPT16K & WR & Protect Main Flash [16K to 16+4K) from erasing and programing.\\ \hline
        5:5 & WPT12K & WR & Protect Main Flash [12K to 12+4K) from erasing and programing.\\ \hline
        4:4 & WPT8K & WR & Protect Main Flash [8K to 8+4K) from erasing and programing.\\ \hline
        3:3 & WPT4K & WR & Protect Main Flash [4K to 4+4K) from erasing and programing.\\ \hline
        2:2 & WPT0K & WR & Protect Main Flash [0K to 0+4K) from erasing and programing.\\ \hline
        1:0 & LATENCY & WR & Latency time for different system clock.\newline 0x0: FREQ\_0\_4M. When system clock is 0~4MHz, LATENCY should be configured as this value.\newline 0x1: FREQ\_4\_8M. When system clock is 4~8MHz, LATENCY should be configured as this value.\newline 0x2: FREQ\_8\_16M. When system clock is 8~16MHz, LATENCY should be configured as this value.\newline 0x3: FREQ\_16\_32M. When system clock is 16~32MHz, LATENCY should be configured as this value.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SR}
Address: 0x40004004. Reset: 0x00000000
\newline 
Status Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:11 & Reserve & RO & Reserve.\\ \hline
        10:3 & ECCSYND & RO & Flash ECC error syndrome.\\ \hline
        2:1 & ECCERR & RO & ECC State.\newline 0x0: NOERR\newline 0x1: ERR1B. 1-bit ECC error occurres when read Flash\newline 0x2: ERR2B. 2-bit ECC error occurres when read Flash\newline 0x3: INVALID\\ \hline
        0:0 & BUSY & RO & Busy state indicate if there is operation of erasing/programing/reading Flash.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{FLSERRADDR}
Address: 0x40004008. Reset: 0x00000000
\newline 
FLASH ECC Error Address Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:0 & ADDR & RO & When Flash ECC error occurs, this register stores where data is error in Flash.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{CMDR}
Address: 0x4000400C. Reset: 0x00000000
\newline 
Flash Operation Command Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:3 & Reserve & RO & Reserve.\\ \hline
        2:0 & CMD & WR & Setect Flash operation command.\newline 0x1: READ\newline 0x2: PROG\newline 0x3: ERASE\_SECTOR\newline 0x4: ERASE\_CHIP\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{STARTR}
Address: 0x40004010. Reset: 0x00000000
\newline 
Start Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:31 & START & WR & Writting 1 to excute cmd in CMD register. Hardwre set it to 0 when the excution has finished.\\ \hline
        30:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{BPROGER}
Address: 0x4000401C. Reset: 0x00000000
\newline 
Byte Program Enable Register.
The 8 bits of this register are corresponded with the 8 bytes of DATAH/LR.
If writing into this register 0xFF, all bytes of DATAH/LR will be written into Flash when PROG command is effective. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:8 & Reserve & RO & Reserve.\\ \hline
        7:7 & BPROGER7 & WR & Program Byte 7 Enable.\\ \hline
        6:6 & BPROGER6 & WR & Program Byte 6 Enable.\\ \hline
        5:5 & BPROGER5 & WR & Program Byte 5 Enable.\\ \hline
        4:4 & BPROGER4 & WR & Program Byte 4 Enable.\\ \hline
        3:3 & BPROGER3 & WR & Program Byte 3 Enable.\\ \hline
        2:2 & BPROGER2 & WR & Program Byte 2 Enable.\\ \hline
        1:1 & BPROGER1 & WR & Program Byte 1 Enable.\\ \hline
        0:0 & BPROGER0 & WR & Promgram Byte 0 Enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{ADDR}
Address: 0x40004020. Reset: 0x00000000
\newline 
Flash Operation Address 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:0 & ADDR & WR & Flash erase/program operation address\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DATALR}
Address: 0x40004024. Reset: 0x00000000
\newline 
Flash Low 32bit Data Regiser. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:0 & DATAL & WR & Low 32bit of a 64bit-program.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DATAHR}
Address: 0x40004028. Reset: 0x00000000
\newline 
Flash High 32bit Data Regiser. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:0 & DATAH & WR & High 32bit of a 64bit-program.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IFR}
Address: 0x40004034. Reset: 0x00000000
\newline 
Interrupt Status Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:5 & Reserve & RO & Reserve.\\ \hline
        4:4 & ERRWPTF & RO & Error interrupt flag, when program/erase areas where writing protection valid.\\ \hline
        3:3 & ERRPOGF & RO & Error interrupt flag, when AHB trys to program Flash.\\ \hline
        2:2 & EOEF & RO & End of erasing Flash interrupt flag\\ \hline
        1:1 & EOPF & RO & End of programming Flash interrupt flag\\ \hline
        0:0 & ERRECCF & RO & ECC error interrupt flag\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IER}
Address: 0x40004038. Reset: 0x00000000
\newline 
Interrupt Enable Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:5 & Reserve & RO & Reserve.\\ \hline
        4:4 & ERRWPTE & WR & When program/erase areas where writing protection valid, report Flash interrupt.\\ \hline
        3:3 & ERRPRGE & WR & Report Flash interrupt when AHB trys to program Flash.\\ \hline
        2:2 & EOEE & WR & Report Flash interrupt when finishing Flash erasing.\\ \hline
        1:1 & EOPE & WR & Report Flash interrupt when finishing Flash programming.\\ \hline
        0:0 & ERRECCE & WR & Flash ECC error interrupt enable\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{ICLR}
Address: 0x4000403C. Reset: 0x00000000
\newline 
Interrupt Clear Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:5 & Reserve & RO & Reserve.\\ \hline
        4:4 & ERRWPTCLR & WO & Write 1 to clear ERRWPTCLR.\\ \hline
        3:3 & ERRPGCLR & WO & Write 1 to clear ERRPOGCLR.\\ \hline
        2:2 & EOECLR & WO & Write 1 to clear EOECLR.\\ \hline
        1:1 & EOPCLR & WO & Write 1 to clear EOPCLR.\\ \hline
        0:0 & ERRECCCLR & WO & Write 1 to clear ERRECCF.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{TSETR0}
Address: 0x40004040. Reset: 0x00774466
\newline 
Timing Setting Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & Reserve & RO & Reserve.\\ \hline
        23:20 & TRCVEC & WR & Chip erase recovery time. Please refer to "Flash Operation Time".\\ \hline
        19:16 & TRCVES & WR & Sector erase recovery time. Please refer to "Flash Operation Time".\\ \hline
        15:12 & TERASEC & WR & Chip erase time. Please refer to "Flash Operation Time".\\ \hline
        11:8 & TERASES & WR & Sector erase time. Please refer to "Flash Operation Time".\\ \hline
        7:4 & TNVSES & WR & Sector erase setup time. Please refer to "Flash Operation Time".\\ \hline
        3:0 & TWUP & WR & Wake up time from Flash deepsleep mode to any Flash operation. Please refer to "Flash Operation Time".\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{TSETR1}
Address: 0x40004044. Reset: 0x00056546
\newline 
Timing setting Register1 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:20 & Reserve & RO & Reserve.\\ \hline
        19:16 & TRCVPRG & WR & Program recovery time. Please refer to "Flash Operation Time".\\ \hline
        15:10 & TPRG & WR & Program time. Please refer to "Flash Operation Time".\\ \hline
        9:4 & TPGS & WR & Program signal setup time. Please refer to "Flash Operation Time".\\ \hline
        3:0 & TNVSPRG & WR & Program setup time. Please refer to "Flash Operation Time".\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{TRIMR0\_RES}
Address: 0x40004060. Reset: 0x80AA5088
\newline 
Flash Trim Parameters 0 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{TRIMR1\_RES}
Address: 0x40004064. Reset: 0xC4808080
\newline 
Flash Trim Parameters 1 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:31 & rameccensr & RO & \\ \hline
        30:0 & val & WR & \\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{NVR4KEYR\_RES}
Address: 0x40004070. Reset: 0x00000000
\newline 
NVR4KEY Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:0 & NVR4KEY & WR & NVR4 section key, the value comes from 0x10648, 31bit~0bit.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{NVR3KEYR\_RES}
Address: 0x40004074. Reset: 0x00000000
\newline 
NVR3KEY Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:0 & NVR3KEY & WR & NVR3 section key, the value comes from 0x10400, 31bit~0bit.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{FLSINJLR}
Address: 0x40004080. Reset: 0x00000000
\newline 
Flash ECC Injection Low 32 bits Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:0 & FLSECCINJL & WR & Low 32 bits of 72 bits ECC injection.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{FLSINJMR}
Address: 0x40004084. Reset: 0x00000000
\newline 
Flash ECC Injection Middle 32 bits Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:0 & FLSECCINJM & WR & Middle 32 bits of 72 bits ECC injection.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{FLSINJHR}
Address: 0x40004088. Reset: 0x00000000
\newline 
Flash ECC Injection High 8 bits Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:8 & Reserve & RO & Reserve.\\ \hline
        7:0 & FLSECCINJH & WR & High 8 bits of 72 bits ECC injection.\\ \hline
		\end{xtabular}
	\end{center}

FMC address end \newline
PMU address start \newline
\subsubsection{STANDBYR}
Address: 0x40005000. Reset: 0x00000000
\newline 
STANDBY Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & STANDBY & WO & Setting this bit to jump into stanyby mode.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{WKUPCR}
Address: 0x40005004. Reset: 0x00000320
\newline 
Standby Wakeup Control Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:10 & Reserve & RO & Reserve.\\ \hline
        9:9 & LINOUTWKUPEN & WR & Enable LINOUT wakeup.\\ \hline
        8:8 & LININWKUPEN & WR & Enable LININ wakeup.\\ \hline
        7:6 & Reserve & RO & Reserve.\\ \hline
        5:0 & WKUPTH & WR & Wakeup time threshold = WAKETH * (1/256k). When LIN\_IN/OUT recessive level is longer than this time, chip will jump out STANDBY mode.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{UPDATER}
Address: 0x40005008. Reset: 0x00000000
\newline 
Wakeup Parameter Update Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & UPDATE & WR & Update LIN wakeup filter configuration.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{FILCR}
Address: 0x4000500C. Reset: 0x00000221
\newline 
Wakeup Filter Control Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:12 & Reserve & RO & Reserve.\\ \hline
        11:8 & POTH & WR & LIN wakeup signal positive filter threshold. Positive filter time = POTH * (1/256k).\\ \hline
        7:4 & NETH & WR & LIN wakeup signal negtive filter threshold. Negitive filter time = NETH * (1/256k).\\ \hline
        3:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & FILEN & WR & LIN wakeup signal filter enable.\\ \hline
		\end{xtabular}
	\end{center}

PMU address end \newline
